As the reliance on secure memory environments permeates across applications, memory encryption is used to ensure memory security. However, most effective encryption schemes, such as the widely used AES-CTR, inherently introduce extra overheads, including those associated with counter storage and version number integrity checks. Moreover, encryption only protects data content, and it does not fully address the memory access pattern leakage. While Oblivious RAM (ORAM) aims to obscure these patterns, its high performance costs hinder practical applications. We introduce Secure Scattered Memory (SSM), an efficient scheme provides a comprehensive security solution that preserves the confidentiality of data content without traditional encryption, protects access patterns, and enables efficient integrity verification. Moving away from traditional encryption-centric methods, SSM offers a fresh approach to protecting data content while eliminating counter-induced overheads. Moreover, SSM is designed to inherently obscure memory access patterns, thereby significantly enhancing the confidentiality of memory data. In addition, SSM incorporates lightweight, thus integrated mechanisms for integrity assurance, protecting against data tampering. We also introduce SSM+, an extension that adapts Path ORAM to offer even greater security guarantees for both data content and memory access patterns, demonstrating its flexibility and efficiency. Experimental results show that SSM incurs only a 10% performance overhead compared to non-protected memory and offers a 15% improvement over AES-CTR mode memory protection. Notably, SSM+ provides an 20% improvement against Path ORAM integrated with Intel SGX under the highest security guarantees.

With the recent emphasis on Parallel and Distributed Computing topics in the Computer Science Curricula 2013, instructors are increasingly incorporating these topics into their undergraduate courses. Unfortunately, many universities lack the dedicated computing resources to provide hands-on experiences in this area. This workshop guides attendees through the open source WorkQueue software to teach parallel and distributed computing principles to undergraduate students. WorkQueue is a distributed master worker framework developed by the Cooperative Computing Lab at the University of Notre Dame. WorkQueue is well-suited for inclusion in undergraduate courses due to the ease of use and deployment on a wide range of computer systems, low administrative overhead, and scalability. WorkQueue can be deployed on any system, from a small Raspberry Pi cluster to a high-performance grid computing environment. This workshop walks attendees through the use of WorkQueue with three demonstrations: a "live demo" such as would be used to engage students in the classroom with a hands-on introduction to distributed computing principles, and a guided "tour" through two lab assignments. The first lab assignment will give attendees a hands-on example of a simple distributed computing problem from implementation to deployment. The second lab will demonstrate WorkQueue MapReduce, a simple framework that can be used to introduce the MapReduce programming model without the overhead of a Hadoop cluster or equivalent. A laptop is required to participate in the workshop; the presenters will provide a pre-configured Linux VirtualBox virtual machine to facilitate software setup, or attendees can use their own Linux installations.

We consider the design of stochastic computing (SC) hardware based on spintronic devices. SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance. When compared to charge-based devices, spin-based devices could be lower energy, nonvolatile, etc. However, spin-based devices can be fundamentally more error prone than charge-based devices. The marriage of SC architectures and spin-based devices has the potential to produce information processing systems that are robust, low energy, and nonvolatile. In this paper, we investigate SC hardware comprised of nanomagnetic logic (NML) devices. NML is a “beyond-CMOS” technology that uses bistable magnets to store, process, and move binary information. We introduce new NML circuit structures that exploit unique features of the technology to efficiently realize hardware components required for an SC system (e.g., random number generation). We also benchmark NML-based SC circuits against other implementations, and illustrate how features that are unique to NML (e.g., inherent pipelining) can lead to improved performance. Our results indicate NML SC implementations achieve smaller area footprints with reduced energy and delay when compared to CMOS equivalents.

Field-coupled nanomagnets can offer significant energy savings at iso-performance versus CMOS equivalents. Magnetic logic could be integrated with CMOS, operate in environments that CMOS cannot, and retain state without power. Clocking requirements lead to inherently pipelined circuits, and high throughput further improves application-level performance. However, bit conflicts -- that will occur in defect free, pipelined ensembles -- can make non-volatile logic volatile. Assuming a field-based clock, we present hardware designs to improve steady state non-volatility, and explain how design enhancements could increase clock energy. We then suggest materials-related design levers that could simultaneously deliver non-volatility and low clock energy.

We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic — or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.

Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, 'Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input-output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.' This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain-using both the NML design space and a discussion of clocking as context-how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

Quoting the International Technology Roadmap for Semiconductors (ITRS) 2009 Emerging Research Devices section, ‘Nanomagnetic logic (NML) has potential advantages relative to CMOS of being non-volatile, dense, low-power, and radiation-hard. Such magnetic elements are compatible with MRAM technology, which can provide input–output interfaces. Compatibility with MRAM also promises a natural integration of memory and logic. Nanomagnetic logic also appears to be scalable to the ultimate limit of using individual atomic spins.’ This article reviews progress toward complete and reliable NML systems. More specifically, we (i) review experimental progress toward fundamental characteristics a device must possess if it is to be used in a digital system, (ii) consider how the NML design space may impact the system-level energy (especially when considering the clock needed to drive a computation), (iii) explain—using both the NML design space and a discussion of clocking as context—how reliable circuit operation may be achieved, (iv) highlight experimental efforts regarding CMOS friendly clock structures for NML systems, (v) explain how electrical I/O could be achieved, and (vi) conclude with a brief discussion of suitable architectures for this technology. Throughout the article, we attempt to identify important areas for future work.

This article quantitatively considers the performance of nanomagnetic logic circuits within the context of realistic drive circuitry. We also demonstrate how one of the five fundamental tenets of digital logic---preventing unwanted feedback---can be satisfied by realistic drive circuitry. More specifically, different types of multiphase clocks are investigated and compared. Initial projections suggest that even with drive circuitry overhead, nanomagnet logic can outperform subthreshold CMOS in terms of energy delay product---and paths to lower power exist.

We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.

We demonstrate that in circuits and systems comprised of nanoscale magnets, magnet shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e. so it is not at a maximum when a device is magnetized along its hard axis). In clocked systems, we can leverage this barrier shift to make AND or OR gates that are not majority-based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper we report and discuss: (i) micromagnetic simulations that illustrate how magnet shape can facilitate non-majoritygate- based, reduced footprint logic, (ii) preliminary fabrication and testing results which illustrate that shape engineering can induce energy barrier shifts, and (iii) additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.

Circuits based on magnetic logic have shown great promise as an extremely low power alternative to CMOS based circuits. However, the success or failure of such circuits hinges on the existence of a locally controllable and low power clock field. Existing work has largely assumed the availability of such a clock field that would be almost impossible to fabricate or that exhibits an ideal distribution in space. This paper uses a fabricatable clock structure proposed in [10] as the basis to investigate all possible non-ideal properties (due to fabrication limitations and variations) of the resulting clock field. How such a clock impacts the logical correctness of a magnetic circuit element is verified via micromagnetic simulation. The impact on performance and power is also considered.

This paper examines how realistic implementations of the drive circuitry needed to control circuit elements made from nano-scale magnets can affect system-level energy and performance. Expected non-uniform clock fields, clock field discontinuities and out-of-plane fields are all considered. We find that realistic fabrication mechanisms should not inhibit logical correctness and that this technology appears capable of outperforming low power CMOS equivalents with similar energy requirements - and paths to additional energy savings exist.

This paper looks at designing circuit elements that will be constructed with nanoscale magnets within the Quantum-dot Cellular Automata (QCA) computational paradigm. In magnetic QCA (MQCA) logical operations and dataflow are accomplished by manipulating the polarizations of nanoscale magnets. Wires and gates have already been experimentally demonstrated at room temperature. However, to realize more complex circuits - and eventually systems - more than just wires and gates in isolation are required. For example, gates must be inter-connected, signals must cross, etc. All structures must be controlled by the envisioned drive circuitry. In this paper, structures that will facilitate these circuit-level tasks are presented for the first time.

This paper looks at circuits and systems made from nanoscale magnets. We leverage physical level simulation to show how to extend initial experimental work-where wires and gates with nanometer feature sizes have been demonstrated at room temperature - to show how one might make design tradeoffs to improve both the performance and reliability of more complex systems.

We introduce SWAGES, a distributed agent-based Alife simulation and experimentation environment that uses automatic dynamic parallelization and distribution of simulations in heterogeneous computing environments to minimize simulation times. SWAGES allows for multi-language agent definitions, uses a general plug-in architecture for external physical and graphical engines to augment the integrated SimWorld simulation environment, and includes extensive data collection and analysis mechanisms, including filters and scripts for external statistics and visualization tools. Moreover, it provides a very flexible experiment scheduler with a simple, web-based interface and automatic fault detection and error recovery mechanisms for running large-scale simulation experiments.