We report on a numerical study of polymer network formation of asymmetric biomimetic telechelic polymers with two reactive ends based on a self-assembling collagen, elastin or silk-like polypeptide sequence. The two reactive ends of the polymer can be activated independently using physicochemical triggers such as temperature and pH. We show, using a simple coarse grained model that the order in which this triggering occurs influences the final morphology. For both of collagen-silk and elastin-silk topologies we find that for relatively short connector chains the morphology of the assembly is greatly influenced by the order of the trigger, whereas for longer chains the equilibrium situation is more easily achieved. Moreover, self-assembly is greatly enhanced at moderate collagen interaction strength, due to facilitated binding and unbinding of the peptides. This finding indicates that both the trigger sequence and strength can be used to steer self-assembly in these biomimetic polymer systems.

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area- and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores; microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm2 and 8.6 mm2, respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

A study of parasitic bipolar junction transistor effects in single pocket thin film siliconon-insulators (SOI) nMOSFETs has been carried out. Characterization and simulation results show that parasitic bipolar junction transistor action is reduced in single pocket SOI MOSFETs in comparison to homogeneously doped conventional SOI MOSFETs. A novel Gate-Induced-Drain-Leakage (GIDL) current technique was used to characterize the SOI MOSFETs. 2 - D simulations were carried out to analyze the reduced parasitic bipolar junction effect in single pocket thin film SOI MOSFETs.

Mesenteric fat is known to undergo inflammatory changes after 2,4,6,-trinitrobenzensulphonic acid (TNBS)–induced colitis. Neurotensin (NT) and neurotensin receptor 1 (NTR1) have been shown to play a major role in the pathogenesis of intestinal inflammation. This led us to explore whether NT and NTR1 are expressed in the mesenteric fat depots during TNBS-induced colitis and whether NT participates in the increased interleukin (IL)–6 secretion in this inflammatory response. TNBS-induced inflammation in the colon increases NT and NTR1 expression in mesenteric adipose tissues, including mesenteric preadipocytes. Compared with wild-type mice, NT knockout (KO) mice have reduced TNBS-induced colitis accompanied by diminished inflammatory responses in mesenteric adipose tissue. Specifically, IL-6 and p65 phosphorylation levels in mesenteric fat of NT KO mice are also reduced compared with wild-type mice. Mouse 3T3-L1 preadipocytes express NTR1 and its expression is increased after stimulation of preadipocytes with proinflammatory cytokines. NT stimulation of 3T3-L1 preadipocytes overexpressing NTR1 causes PKCδ phosphorylation and IL-6 secretion in a time- and dose-dependent fashion. Moreover, NT-mediated IL-6 expression is nuclear factor–κB and PKCδ dependent. We also found that supernatants from NT-exposed 3T3-L1-NTR1 preadipocytes and mesenteric fat obtained from wild-type mice 2 days after TNBS administration stimulate an IL-6–dependent macrophage migration measured by a macrophage migration assay, whereas this response is reduced when mesenteric fat from NT KO mice is used. These results demonstrate an important role for NT in acute colitis and adipose tissue inflammation associated with experimental colitis that involves direct NT proinflammatory responses in preadipocytes.

to determine the impact of TLR signaling on CAC (n=5).Colonoscopy was used to follow tumor progression and the development of inflammation.Inflammation and tumor grade were evaluated histologically and colonic levels of IL-12p40 and TNFα mRNA were measured by real-time PCR.Nuclear β-catenin levels and NF-kB phosphorylation were determined by immunohistochemistry. Results: AOM-treated (6 weekly injections) IL-10-/-mice developed colitis and displayed highly penetrant tumor formation under SPF conditions, while WT mice showed no evidence of intestinal inflammation and had minimal tumor formation.AOM-treated IL10-/-mice showed a dramatic increase in colon tumor multiplicity and progression compared to WT mice.Tumor multiplicity increased 20-fold while progression from low to high-grade/invasive carcinoma increased by ~70% in IL10-/-compared to WT mice.These tumors showed increased nuclear β-catenin accumulation and the presence of phosphorylated RelA.B. vulgatus mono-associated IL10-/-mice failed to develop significant intestinal inflammation and showed greatly reduced tumor formation.AOM-treated IL10-/-; MyD88-/-mice showed reduced colonic expression of TNFα and IL12p40 mRNA and were devoid of neoplastic lesions compared to AOM-treated IL10-/-mice.Conclusions: Bacterial-induced intestinal inflammation correlates with the progression of colon cancer in AOM-treated IL-10-/-mice.The TLR/MyD88 signaling pathway is essential for the development of CAC.

The paper presents a method for assessing the impact of interconnects on dynamic system level performance. The method is applied to the analysis of the impact of interconnect parasitic resistance and capacitance on the performance of different circuit types at the 45-nm technology node. It is observed that the interconnect capacitance dominates circuit performance at short interconnect lengths. The interconnect resistance influences low-power (high-speed) circuit speed only for critical wire lengths longer than 360 /spl mu/m (180 /spl mu/m). Within the investigated interconnect lengths, the interconnect resistance has virtually no impact on the switching energy of the test circuit. The results indicate that for low-power circuits, the high interconnect resistance is not a serious issue at the 45-nm technology node.

Gate length variability is the dominant cause of performance variability in nanometer IC technologies. In this work, layout design techniques for reducing gate length variability are presented. It involves making choices in the layout design that improve the dimensional control of the lithographic process. By relaxing the minimum pitch and by reducing the proximity variations for the gate lines, the litho-process is improved. Litho-simulations and statistical circuit simulations are done on various circuit layouts to estimate the resulting improvement in the gate length spreads and corresponding delay spreads. The litho-driven layouts show a factor of two improvement in the delay spread at the cost of small area and speed penalty.

Using a novel gate-induced-drain-leakage (GIDL) current technique and two-dimensional (2-D) simulations, single pocket (SP) SOI MOSFETs have been shown to exhibit reduced floating body effects compared to the homogeneously-doped channel (conventional) SOI MOSFETs. The GIDL current technique has been used to characterize the parasitic bipolar transistor gain for both conventional and SP-SOI MOSFETs. From 2-D device simulations, the lower floating body effects in SP-SOI MOSFETs are analyzed and compared with the conventional MOSFETs.

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.

This paper presents results on the characterization Of Lateral Asymmetric Channel (LAC) thin film silicon-on insulator (SOI) MOSFETs. These devices are compared with conventional SOI MOSFETs having uniform channel doping. The measurements have been taken for a number of channel lengths, silicon film thicknesses, and tilt angles of implantation. The aspects studied include threshold voltage roll-Off, kink effect, gate induced drain leakage (GIDL) and parasitic bipolar transistor action. Measurements have been supplemented by device simulations. The LAC devices show excellent characteristics, with many advantages over the conventional devices.

There has been increasing interest in polysilicon thin film transistors (TFTs) for high-performance applications, particularly in high-resolution displays. For these applications, the primary requirement is that the TFTs have a low threshold voltage, low and stable leakage current and reasonably high carrier mobility. The poly-Si TFTs typically have sufficiently large mobilities to be used for high-drive and moderately high-frequency applications. However, since low temperatures are used in poly-Si TFT fabrication, both semiconducting and insulating layers are of poorer quality than those used in crystalline-Si technology. Consequently, long term TFT stability is an important issue. A considerable amount of research has focused on the stability of poly-Si TFTs. The instabilities are basically associated with hot carrier injection and degradation, negative gate bias instability and gate-induced carrier injection and trapping (Young, 1996). This leads to degradation of several device parameters such as threshold voltage, mobility, transconductance, and subthreshold slope. The work presented here is a comprehensive study of degradation in low temperature (/spl les/600/spl deg/C) poly-Si TFTs due to high-field, hot-carrier and ionizing radiation stressing. This unified approach makes it possible to identify the key reasons for degradation. Furthermore, a systematic study of the dependence on device geometry, as reported here, also helps understanding of the degradation mechanisms.

In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel Gate-Induced-Drain-Leakage (GIDL) current technique. The parasitic bipolar current gain beta has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2-D device simulations.