Nowadays, High-Performance Computing (HPC) systems need to deliver computational performance by processing complex applications and workloads at high speeds in parallel. To provide computing power, Multiprocessor System-on-Chip, the main design paradigm, is scaled with advanced technology nodes and even with heterogeneity. These improvements open up more design possibilities, leading to an increase in its complexity. Therefore, chip designers are facing unprecedented challenges to find the best Power, Performance, and Area architectural configurations, inducing a Design Space Exploration problem. This work proposes a complete framework to ease the next generation of HPC processor designs. By combining competitive simulators VPSim and McPAT for a realistic estimation of Key Performance Indicators, with a time-consuming simulation-adapted exploration algorithm such as Bayesian Optimization, we leveraged an Automated Design Space Exploration for efficient HPC processor designs based on ARMv8 architecture. We have also demonstrated the potential of Bayesian Optimization to reach a similar or even larger Pareto front than Genetic Algorithm while being around 2 × to 5 × sample-efficient. Furthermore, the diversity of the obtained Pareto-front enables deep analysis of relevant architectural parameters that significantly impact design performances and thus, empowering architects’ knowledge for further targeted design exploration and design choices.

Normalizing flows are generative models that show poor performance on out-of-distribution (OOD) detection tasks with a likelihood-based test. In this study we focus on the "approximate mass" metric. We show that while it improves OOD detection performance, it has limitations under a maximum likelihood training. To solve this limitation we modify the training objective by incorporating the approximate mass. It smooths the learnt distribution in the vicinity of training in-distribution data. We measure an average of 97.6% AUROC in our experiments on different benchmarks, showing an improvement of 16% with respect to the best baseline we tested against.

Artificial Intelligence (AI) is now everywhere and its domains of application grow every day. But its demand in data and in computing power is also growing at an exponential rate, faster than used to be the “Moore's law”. The largest structures, like GPT-3, have impressive results but also trigger questions about the resources required for their learning phase, in the order of magnitude of hundreds of MWh. Once the learning done, the use of Deep Learning solutions (the “inference” phase) is far less energy demanding, but the systems are often duplicated in quantities (e.g. for consumer applications) and reused multiple times, so the cumulative energy consumption is also important. It is therefore of paramount importance to improve the efficiency of AI solutions in all their lifetime. This can only be achieved by combining efforts on several domains: on the algorithmic side, on the codesign application/algorithm/hardware, on the hardware architecture and on the (silicon) technology for example. The aim of this short tutorial is to raise awareness on the energy consumption of AI and to show different tracks to improve this problem, from distributed and federated learning, to optimization of Neural Networks and their data representation (e.g. using “Spikes” for information coding), to architectures specialized for AI loads, including systems where memory and computation are near, and systems using emerging memories or 3D stacking.

This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip.

This paper presents a 2-layer 3D stacked Back Side Illuminated vision chip performing high speed programmable parallel computing by exploiting in-focal-plane pixel readout circuits. The proposed circuit exhibits a 5500fps frame rate, 5 times higher than previous works without reducing ADC resolution. It allows heterogeneous parallel computations on up to 31×31 inter-pixels neighborhoods in a single chip.