High-performance Ag-Se-based n-type printed thermoelectric (TE) materials suitable for room-temperature applications have been developed through a new and facile synthesis approach. A high magnitude of the Seebeck coefficient up to 220 mu V K-1 and a TE power factor larger than 500 mu W m(-1) K-2 for an n-type printed film are achieved. A high figure-of-merit ZT similar to 0.6 for a printed material has been found in the film with a low in-plane thermal conductivity kappa(F) of similar to 0.30 W m(-1) K-1. Using this material for n-type legs, a flexible folded TE generator (flexTEG) of 13 thermocouples has been fabricated. The open-circuit voltage of the flexTEG for temperature differences of Delta T = 30 and 110 K is found to be 71.1 and 181.4 mV, respectively. Consequently, very high maximum output power densities p(max) of 6.6 and 321 mu W cm(-2) are estimated for the temperature difference of Delta T = 30 K and Delta T = 110 K, respectively. The flexTEG has been demonstrated by wearing it on the lower wrist, which resulted in an output voltage of similar to 72.2 mV for Delta T approximate to 30 K. Our results pave the way for widespread use in wearable devices.

High mobility, electrolyte-gated FETs (EGFETs), based on precursor-derived oxide semiconductors, enable the possibility of achieving printed and low voltage (<;2 V) operated circuits. These EGFETs can also be realized with displaced-gate geometries. However, the displaced-gate devices are typically slow due to high electrolyte resistance resulting from the large gate-channel distances. Here, we show that a thin insulating (composite solid polymer electrolyte) layer and a top-gate geometry can largely overcome this limitation, a comprehensive comparison between the displaced-gate and the top-gate devices has been provided. In order to facilitate circuit design, we have successfully developed accurate models to predict the behavior of these top-gate EGFETs. The importance of our modeling approach is further enhanced by the fact that appropriate predictive modeling strategies for printed circuits, especially for those that are based on oxide semiconductors, are largely missing. Unlike existing transistor models that do not cover all voltage regimes (below, near, and above threshold), we propose a new modeling methodology that matches very well with the measured data, is continuous and smooth over the entire voltage range, and can be easily incorporated into SPICE simulators.

The temperature dependence of the gate leakage current has been developed for Double Gate (DG) MOSFETs. This model is compared with experimental data measured in Trigate MOSFETs at various temperatures with SiON as a dielectric material and SiO2 as an interfacial layer. The gate leakage current measurements at different temperatures show two different transport mechanisms, direct tunneling (DT) gate leakage and Trap-Assisted-Tunneling (TAT) current. Our analysis based on leakage current measurements in the above threshold regime for different temperatures shows that the DT current is clearly dominant over the TAT, while the opposite happens below threshold. Our model is able to explain the gate tunneling current in terms of gate voltage for different temperatures. The results of the DT current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements.

We have experimentally investigated the threshold voltage shift due to negative bias temperature instability (NBTI). The NBTI stress in the absence of self-heating (SH) is performed at two different temperatures, i.e., T = 25°C and 125°C, at bias conditions: gate voltage V gs = -2& V and drain voltage V ds = 0 V. To evaluate the effect of NBTI in the presence of SH, the stress is performed at room temperature and at V gs = -2 V and V ds = -1 V. It has been observed that NBTI in the presence of SH causes a significant shift in the threshold voltage.

This paper presents Double Gate (DG) MOSFET models of the temperature dependences as part of a compact analytical model for the direct tunneling gate leakage and Trap-Assisted-Tunneling (TAT) current. We compare the adapted modeling calculations with experimental data of the gate leakage current in Trigate MOSFETs at various temperatures. The results of the direct tunneling current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements with SiON as a gate oxide material. Our analysis above threshold voltage shows that the direct tunneling gate leakage current is clearly dominant over the TAT, while it is the opposite below threshold.

In this letter, we propose to introduce the notion of equivalent capacitance and to generalize the so-called equivalent-thickness concept to model arbitrary shapes of lightly doped nonplanar multigate MOSFETs, without the need to introduce any unphysical parameter. These definitions, which merely map a multigate geometry into the symmetric double-gate (DG) MOSFET topology, have been validated by extensive comparison with 3-D numerical simulations of quadruple-gate, triple-gate (TG), triangular gate, cylindrical gate-all-around, and DG Fin Field Effect Transistors (FinFETs). Based on this modeling approach, any multigate architecture inherits of the fundamental relationships that have been developed for planar DG MOSFETs, including the normalization of all electrical quantities that considerably simplifies its analysis. In addition, considering a constant mobility, we find that the model can predict electrical characteristics of FinFETs from 275 to 425 K, without the need for any additional parameters. Finally, we were able to predict electrical measurements of a TG MOSFET, making of this generic model an interesting candidate for a design-oriented compact model for arbitrary multigate MOSFETs geometries.

For the first time we have reported thermal failure of FinFET devices related to fin thickness mismatch, under the normal operating condition. Pre and post failure characteristics are investigated. Furthermore, a detailed physical insight towards heat transport in a complex back-end of line (BEOL) of a logic circuit network is given for FinFET and extreme thin silicon on insulator (ETSOI) devices. Self heating behavior of both the FinFET and ETSOI devices is compared. Moreover, layout, device and technology design guidelines (based on complex 3D TCAD) are given for robust thermal management and electrical overstress / electrostatic discharge (EOS/ESD) reliability.

In this letter, we present an experimental evaluation of self-heating (SH) effects (SHEs) using S-parameter measurements for both n- and p-type SOI FinFETs. It is revealed that NFETs show a stronger SHE than PFETs, which ultimately leads to a higher variation of the intrinsic gain in NFETs. Our results also show that long-channel devices typically used in analog design show pronounced negative output conductance, which consequently leads to a negative intrinsic gain at low frequencies. Another implication of the strong SHE is that the interdie variability of the isothermal intrinsic gain gets “amplified” at lower frequencies due to SH.

A comprehensive modeling framework for 3D multigate FETs (MugFETs), applicable to FinFETs as well as gate-all-around MugFETs is presented. We use the double-gate FinFET as our reference device and solve the 2D-Laplace equation with the help of conformal mapping techniques. The 2D solution is then extended to 3D structures with the appropriate use of characteristic lengths. The results have been validated with 3D TCAD simulations from ATLAS device simulator. In addition DC-measurements on trigate SOI FinFETs for different fin width have been performed with special emphasis on the subthreshold and linear current regime behaviour. Our measured results agree reasonably well with the model.

We investigate cross-correlations in the tunneling currents through two parallel quantum dots coupled to independent electrodes and gates and interacting via an inter-dot Coulomb interaction. The correlations reveal additional information, beyond what can be learned from the current or conductance, about the dynamics of transport processes of the system. We find qualitatively different scenarios for the dependence of the cross-correlations on the two gate voltages. Reducing the temperature below the inter-dot Coulomb interaction, regions of a given sign change from spherical shapes to angular L-shapes or stripes. Similar shapes have been observed in recent experiments.

We investigate the conductance and zero-frequency shot noise of interacting, multilevel quantum dots coupled to leads. We observe that cotunneling assisted sequential tunneling (CAST) processes play a dominant role in the transition region from Coulomb blockade to sequential tunneling. We analyze for intermediate coupling strength the dependence of the conductance due to CAST processes on temperature, coupling constant, and gate voltage. Remarkably, the width of the CAST transport feature scales only with temperature, but not with the coupling constant. While the onset of inelastic cotunneling is associated with a super-Poissonian noise, the noise is even stronger above the threshold for CAST processes.

Motivated by activities of several experimental groups we investigate electron transport through two coherent, strongly coupled quantum dots (``double quantum dots''), taking into account both intra- and inter-dot Coulomb interactions. The shot noise in this system is very sensitive to the internal electronic level structure of the coupled dot system and its specific coupling to the electrodes. Accordingly a comparison between experiments and our predictions should allow for a characterization of the relevant parameters. We discuss in detail the effect of asymmetries, either asymmetries in the couplings to the electrodes or a detuning of the quantum dot levels out of resonance with each other. In the Coulomb blockade region super-Poissonian noise appears even for symmetric systems. For bias voltages above the sequential tunneling threshold super-Poissonian noise and regions of negative differential conductance develop if the symmetry is broken sufficiently strongly.