Vision processor is favorable for edge computing scenarios due to its advantages of high computing efficiency and low power consumption. It can operate various image processing algorithms on a single chip. This paper firstly overviews the progress of vision processor researches in decades. Then, the paper introduces a design of programmable parallel vision processor architecture, which can flexibly implement both computer vision algorithms and deep learning neural network algorithms. A vision processing enhanced RISC instruction set is designed to accelerate the execution of deep learning algorithms. Moreover, this paper introduces a set of algorithm optimization methods from an algorithm/hardware co-design perspective, and deploys algorithms on the vision processor efficiently.
Biomedical signals like Electrocardiogram (ECG), Electroencephalogram (EEG) and photoplethysmography (PPG) are recorded routinely to provide helpful information for early diagnosis of disease. A low power consumption is very important to allow long term ambulatory monitoring with battery powered systems. Direct digital conversion (DDC) technique has been proposed in recent years which emerges the preamplifier and data converters, reducing the complexity of readout chain and thus its power consumption. This paper provides a review on DDC for biopotential signals and bio-optical signals acquisition. The state-of-the-art DDC based readout architectures together with circuit implementations are provided.
This work presents a 0.8~18GHz wideband reconfigurable receiver front end design and simulation with Simulink. The wideband front end can support different bandwidth and operate in a broadband system simultaneously. Simulink has advantages in high level synthesis of receiver design due to the encapsulated blockers that take into account their main circuit limitation. The receiver front end integrates a low noise amplifier (LNA), mixer, tunable low pass filter, variable gain amplifier (VGA) and local oscillator (LO). The wideband receiver front end operated between 0.8~18GHz achieves tunable bandwidth of 500MHz and 1GHz, a total gain of 20dB, a sensitivity of -80dBm, a noise figure (NF) of 5.65dB, an IIP3 of -5.5dBm, and a 3th Chebyshev low pass approximation achieving >16dB attenuation at an offset of 100MHz for the 1GHz bandwidth setting.
Dual active layer (DAL) Mg-doped InZnO thin film transistors (TFTs) are fabricated with ultralow usage of the rare metal In. Optimized DAL MIZO TFTs are obtained by adjusting In-doping, Mg content, and the thickness of two active layers. Compared with conventional single active layer TFTs, the DAL MIZO TFTs showed improved performance in terms of carrier mobility, threshold voltage (Vth), ON-state current (ION), and leakage current (IOFF). The front channel near the gate oxide has a lower Mg-doping and a higher In-doping compared with that of back channel, providing a high carrier concentration (ne) to increase ION. The back channel has a higher Mg-doping and a lower In-doping, providing a low ne to suppress IOFF. Furthermore, the heterojunction potential barrier formed between the two channel layers also helps to suppress the IOFF of the DAL TFTs.
In this paper, single event burnout (SEB)effect is investigated for 700V Double-RESURF SOI LDMOS. SEB mechanism is revealed that parasitic bipolar turn-on and self-maintaining. In first stage, due to holes ionized by a heavy particle, voltage drop along p-well region is increased, giving rise to parasitic bipolar turn-on. In second stage, electrons from the bipolar induces Kirk effect, and cause new hole-electron pairs due to electric field enhanced. New ionized holes flow to P-well, and provide a supplement to base electrode current, which forms positive feedback and makes parasitic bipolar self-maintaining. Compared to single-RESURF structure, the double-RESURF structure has better immunity to SEB effect because of P-top layer. P-top layer provides a path to extract hole current in N-drift region, suppressing parasitic bipolar turn-on and self-maintaining. Experiment result shows that no SEB is observed for the double-RESURF LDMOS device at LET = 86.1MeV‧ mg/cm 2 .
Triple patterning lithography, is a practical method of layout manufacturing under advanced technology node. In triple patterning lithography, the most important thing is layout decomposition. In the process of layout decomposition, proper layout simplification can greatly improve the solving speed, but the simplification of these algorithms used in the industries now are not enough. In this paper, we proposed a new clustering algorithm to further reduce the scale of each conflict graph. Meanwhile, a new color adjustment algorithm between clusters are proposed to maintain or even reduce the decomposition cost. Experimental results show that the proposed algorithm with clustering can achieve an 11% decrease in decomposition cost, and a 26% improvement in solving speed compared with the algorithm without clustering, averagely.
The cryptographic instruction extension based on general processors is a way of implementation of a cryptographic processor. Starting from actual needs, this article abstracts the design problem of the processor into the search problem of data-dependent graph space. Under the constraints of the equivalent alternative graph, we conduct a design space search combined with the practical performance provided by the actual hardware platform. This article takes the AES algorithm as an example to build a platform with Rocket-chip-based processor. Due to the small space, a complete proportional algorithm is used for search. The experimental results show that the explorer can find the design that meets the needs in a short period of time.
As the critical building block of the ternary system, massive research in recent years has mainly been focused on the ternary inverter. Particularly, the tunnel FET (TFET)-based ternary inverter is of great interest due to its small supply voltage (V DD ) and energy-efficient signature. However, it is still problematic for the inverter to obtain stable intermediate state due to the input-voltage-dependent tunneling current. In the paper, a TFET-based ternary inverter with the equiprobable, distinctive and stable electrical states is demonstrated. Moreover, the formation mechanism of the stable intermediate state is investigated in detail. Finally, the impact of V DD on the voltage-transfer characteristics of the ternary inverter is also discussed deeply. This study shows the great application foreground of the TFET-based ternary inverter for the ternary system.
In this paper, the total-ionizing-dose (TID) effects in nanotube tunneling field-effect transistor with bias-induced electron-hole bilayer (EHBNT-TFET) are investigated by 3-D TCAD simulation for the first time. The effects of radiation dose and geometric parameters on TID response, as well as the radiation effect on flicker noise are evaluated in detail. The results show that ON-state current and subthreshold swing are immune to irradiation-induced oxide trap charges and interface traps, while OFF-state current degrades significantly. The TID response is found to strongly depend on the inner-gate diameter and the underlap length between inner-gate and drain. The drain current noise spectral density after ionizing radiation shows an obvious increase due to the existence of interface traps.
In this paper, a 1200 V asymmetric trench SiC MOSFET with an embedded unipolar electron channel for enhanced reverse conduction performance is proposed and investigated by TCAD simulations. For the proposed device, a sidewall N-layer beneath the source-connected dummy gate serves as the reverse current path from the N+ source to the N- drift region. Due to a smaller potential barrier, the cut-in voltage (Vcut-in) of this path is lower than the PN body diode. Therefore, the intrinsic body diode is fully inactivated and the bipolar degradation is eliminated. Meanwhile, the gate to drain charge (QGD) and switching loss are reduced by using the split gate MOSFET structure. As a result, the proposed device has a smaller Vcut-in of 0.94 V compared with 2.69 V of the conventional one. And the QGD and switching loss are reduced by 34.8% and 30.1%, respectively.
This paper presents a low-power boost converter for energy harvesting from a scalable cotton-yarn-based battery. The proposed converter can start up at 700mV. Compared with other start-up strategies, a start-up strategy of sharing the main power NMOS without a start-up transistor is adopted to reduce the chip area. The input voltage range of the converter can reach 4.2V and the output range is 1.8V-5V. The proposed converter is implemented in 0.18 μm BCD process. And the chip area is 616μm × 417μm, which is 4.6% less than using a start-up transistor.
As an important communication infrastructure, the data transmission efficiency of Network-on-Chip (NoC) plays a key role in improving the performance of multi-core systems. A packet and circuit switching mechanism based adaptive transmission network (PCSAT_NET), supporting X-Y routing and Retrograde-Turn routing strategies, which is suitable for mass data transmission is proposed here. It also adopts targeted optimization measures for mass data transmission, including keep-alive and adaptive transmission mechanism. The goal of this architecture is to achieve higher transmission efficiency in a congested data network. Therefore, we deployed a multi-core system based on this network, and experimental results show that compared with the traditional packet and circuit switching mechanism based network, PCSAT_NET could reduce the overall run time by at least 23% when the data network is severely congested and each task competes for computing resources.
In the paper, adoptive RX equalizer is implemented in DDR4 write path to reduce the reflection and ISI which is caused by multi drop channel. The proposed write path is combined with CTLE and LF equalizer based on dual reference decision-feedback equalization (DFE). The proposed write path scheme can improve the 35% voltage margin compared to conventional write path.
Processors based on conventional von Neumann architecture are approaching the memory wall, greatly limiting the development of high energy efficient AI edge devices. Compute-In-Memory (CIM) is a promising candidate to break the memory wall. This paper gives a survey of recent SRAM-CIMs with the focus on the computing methodology and performance of selected SRAM-CIM macros. The on-going trends of recent and further development of CIM technology are also discussed in this work.
The transimpedance amplifier (TIA) is a key component in the analog baseband (BB) of a current-mode receiver (RX). It requires low input impedance (Z in ) and high linearity up to very high frequencies. However, due to the narrow bandwidth (BW) of the Miller-compensated transconductance amplifier (OTA), Z in often peaks at medium frequency (MF), degrading out-of-band (OOB) linearity. This article aims to remove the peak. To this end, an OTA with 44.8dB open-loop gain and 1.8GHz unity-gain loop bandwidth (UGLB) is proposed. It’s based on a two-stage pseudo-differential OTA. Instead of the Miller compensation, which pushes the dominant pole to lower frequency, this paper uses negative capacitance (NC) to push the non-dominant pole to higher frequency, thereby increasing UGLB and phase margin (PM). The TIA, designed and simulated in the TSMC 40nmLP technology, achieves 50MHz BW for 5G sub6GHz wideband RX. Its in-band (IB) and OOB IIP3s are 35.4dBm and 45.2dBm, respectively. Z in is less than 11.4Ω at all frequencies, while consuming 9.4mW from a 1.2V supply.
Piezoelectric resonance sensors, which measure the mass of absorbed materials by detecting the resonance frequency, have wide applications. In this paper, a parity time (PT) symmetric system is presented to improve the sensitivity of piezoelectric resonance sensor. The PT symmetric system exhibits an exceptional point (EP) as the eigenvalues change from complex to real, and the eigenvalues and corresponding eigenstates split up simultaneously. High sensitivity of frequency splitting to small perturbation at EP has important applications in resonance sensing systems. The EP is observed in the PT symmetric system of a piezoelectric resonator coupled with an LCR circuit in this work. With sufficiently small perturbation, the sensitivity of the PT system is ultra-enlarged compared with a traditional resonance sensor. Both theoretical analysis and experimental variation are performed with a humidity sensing system.
A new electric-magnetic-thermal co-simulation method is proposed to optimize the design of SiC GTO module. The proposed co-simulation is a transient method with multiple time scale, which mainly includes software PSpice, ANSYS Q3D and COMSOL. The results show that packaging parasitic parameters adversely affect switching characteristics of SiC GTO. As a result, the junction temperature and case temperature are increased in comparison with no parasitic parameter. When heat dissipation is water cooling, the junction temperature and case temperature rise with gradually declined rising rate until steady temperature of 81°C and 41°C. With air-cooled heat dissipation, the temperature presents approximately linear rise, but the temperature of solder joint exceeds the melting point of Sn-3.5Ag solder (221°C) from 7.3s so that module failure happens.
Silicon carbide MOSFET has been commercialized and applied to industrial and automotive area for many years. Superjunction structure contributes to a good tradeoff between specific on-resistance (R on,sp ) and breakdown voltage (BV). In this article, superjunction structure is applied in thick central oxide gate structure MOSFET (TCOX-MOSFET) to achieve a better performance. A current commercial SiC MOSFET product (AIMW120R060M1H) is also used to make a comparison. The new superjunction MOSFET (SJ-TCOX-MOSFET) has a 72% smaller specific on-resistance compared to the TCOXMOSFET. Additionally, the total gate charge (Q G ) is improved by 56.9% and 89% respectively compared to TCOX-MOSFET and AIMW120R060M1H. The total switching loss (E tot ) is also improved by 26.5% and 42.3% respectively compared to them. The simulation results show that the new SJ-TCOX-MOSFET is a desirable structure.
A new failure mechanism for P-GaN gate HEMT under unclamped-inductive-switching (UIS) stress is revealed in this paper. For the first time, the failure process is divided into two phases: semi-failure phase and full-failure phase. The UIS failure is confirmed consisting of an initial vertical drain-to-substrate leakage current burst in the semi-failure phase and subsequent drain-to-substrate-to-source current runaway with normal gate function in the full-failure phase. According to the revealed failure mechanism, the basic principles for UIS capability improvement are given in this paper and corresponding two protection schemes with drain voltage clamping are investigated.
RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks (DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM device variations and lower precision, the mapping of DNNs to RRAM-based IMC suffers from severe accuracy loss. In this work, we propose a novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy. The digital SRAM macro consists of a small SRAM memory array and an array of multiply-and-accumulate (MAC) units. The non-ideal output from the RRAM macro, due to device and circuit nonidealities, is compensated by adding the precise output from the SRAM macro. In addition, the programmable shifter allows for different scales of compensation by shifting the SRAM macro output relative to the RRAM macro output. We design a silicon prototype of the proposed hybrid IMC architecture in the 65nm SUNY process to demonstrate its efficacy. Experimental evaluation of the hybrid IMC architecture shows up to 21.9%, and 6.5% improvement in post-mapping accuracy over state-of-the-art techniques, at minimal overhead for CIFAR-10 and ImageNet datasets, respectively.
