Control of faceting during epitaxy is critical for nanoscale devices. This work identifies the origins of gaps and different facets during regrowth of InGaAs adjacent to patterned features. Molecular beam epitaxy (MBE) near SiO2 or SiNx led to gaps, roughness, or polycrystalline growth, but metal modulated epitaxy (MME) produced smooth and gap-free "rising tide" (001) growth filling up to the mask. The resulting self-aligned FETs were dominated by FET channel resistance rather than source-drain access resistance. Higher As fluxes led first to conformal growth, then pronounced {111} facets sloping up away from the mask.

For the first time, we report fabrication and characterization of high-performance s-Si1-xGex-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization of s-SiGe fins with WFIN =3.3nm and devices with LG=16nm, in a CMOS compatible process. Using a Si-cap-free passivation, we report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1013cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. We also report the highest performance reported to date among sub-20nm-LG pMOS FinFETs at VDD=0.5V. In addition, hole transport as well as electrostatics, performance and leakage characteristics of SGOI FinFETs for various dimensions are comprehensively studied in this work.

We demonstrate high performance (HP) s-SiGe pMOS finFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. We also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and LG~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe finFETs are strong candidates for future HP and low-power applications.

Contact resistances are directly measured for contacts with sizes from 25 to 330 nm using e-beam based nano-TLM devices. Record low contact resistivities similar to 1.5x10(-9) Omega.cm(2) are extracted from Ni(Pt) silicide contacts on in situ boron-doped Si0.7Ge0.3 with a chemical boron-doping density of 2x10(21)/cm(3). This is very promising for pMOS applications beyond the 10-nm node. A clear dependence of contact resistance on the silicide thickness has also been found.

InGaAs/InP DHBTs are fabricated using electron-beam lithography to define the emitter and base mesas. Emitter mesas 150 nm wide, and base mesas with < 25 nm misalignment to the emitter have been developed. Emitter contacts are prepared through blanket, refractory metal evaporation to obtain emitter contact resistivity rho(ex) = 2 Omega.mu m(2). This low record resistivity, combined with the narrow emitter and base mesas, enables device RF performance of simultaneous f(r) and f(max) of 530 GHz and 750 GHz, respectively, at a power density of > 40 mW/mu m(2).[GRAPHICS]A top-view SEM micrograph of the electron-beam lithography-defined emitter and base contacts, shows narrow mesas and small misalignment between the two layers. (C) 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

We calculate minimum feasible contact resistivities to n-type and p-type InAs and In0.53Ga0.47As. Resistivities were calculated for a range of Schottky barrier heights as well as for the case where the transmission probability is unity (Landauer limit). Calculations are compared with recent experimental data. Experimental contact resistivities for n-In0.53Ga0.47As and n-InAs lie within 2.5:1 of calculated resistivities given generally accepted values of Schottky barrier potential. Computed resistivities in the presence of a barrier are only 3.5:1 to 4:1 above Landauer limits.

The intrinsic lower limit of contact resistivity (ρcLL) for InAs, In0.53Ga0.47As, GaSb, and Si is calculated using a full band ballistic quantum transport approach. Surprisingly, our results show that ρcLL is almost independent of the semiconductor. An analytical model, derived for 1D, 2D, and 3D, correctly reproduces the numerical results and explains why ρcLL is very similar in all cases. Our analysis sets a minimal carrier density required to meet the International Technology Roadmap for Semiconductors call for ρc=10−9 Ω-cm2 by 2023. Comparison with experiments shows there is room for improvement, which will come from optimizing interfacial properties.

We calculate the minimum feasible contact resistivity to n-type and p-type In0.53Ga0.47As, InAs, GaAs, GaSb, InP, and InSb. The calculations consider image force lowering and assume either parabolic or non-parabolic energy dispersion in the semiconductor; their results are compared with recent experimental data. Among significant results, the measured contact resistivity to n-In0.53Ga0.47As at a carrier concentration of 5 × 1019 cm−3 is only 2.3:1 higher than that calculated assuming a 0.2 eV barrier potential, and the measured contact resistivity is only 9.0:1 larger than the Landauer quantum conductivity limit at this carrier concentration. These results indicate that, with the surface preparation procedures presently employed, surface contamination does not markedly increase the interface resistance, and that the transmission coefficient for carriers crossing the interface exceeds 10%.

We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating fτ = 480 GHz and fmax = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz fmax even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (Wgap) to ∼ 10 nm, thereby significantly reducing the gap resistance term (Rgap) in the total base access resistance (Rbb), enabling a high fmax device. Reduction in the total collector base capacitance (Ccb) through undercut in the base mesa below base post further improved fmax. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (Je) without problems of electromigration or contact diffusion under electrical stress [1].

We report InP/In0.53Ga0.47As/InP double heterojunction bipolar transistors (DHBTs) demonstrating simultaneous 460 GHz f and 850 GHz fmax. The devices were fabricated using a triple mesa process with dry-etched, refractory metals for emitter contact formation. The devices incorporate a 35 nm thick InP emitter which enables a wet etch emitter process demonstrating 220 nm wide emitter-base junctions with less than 10 nm undercut in the emitter semiconductor below emitter metal. This reduces the gap between base metal contact and emitter semiconductor causing significant reduction in emitter-base gap resistance (Rgap) component of the total base access resistance (Rbb), leading to an increase in observed fmax. At peak RF performance, the device is operating at 32 mW/m with Je = 19.4 mA/m and Vce = 1.66 V. The devices show a DC common emitter current gain () ~ 20 and VBR,CEO = 3.7 V.

We report InP/In0.53Ga0.47As/InP double heterojunction bipolar transistors (DHBTs) demonstrating simultaneous 460 GHz fτ and 850 GHz fmax. The devices were fabricated using a triple mesa process with dry-etched, refractory metals for emitter contact formation. The devices incorporate a 35 nm thick InP emitter which enables a wet etch emitter process demonstrating 220 nm wide emitter-base junctions with less than 10 nm undercut in the emitter semiconductor below emitter metal. This reduces the gap between base metal contact and emitter semiconductor causing significant reduction in emitter-base gap resistance (Rgap) component of the total base access resistance (Rbb), leading to an increase in observed fmax. At peak RF performance, the device is operating at 32 mW/μm2 with Je = 19.4 mA/μm2 and Vce = 1.66 V. The devices show a DC common emitter current gain (β) ~20 and VBR,CEO = 3.7 V.

Abstract-We report an InPZIn0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz fτ and 800-GHz fmax. The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/μm2 with Jc = 18.4 mA/μm2 and Vce = 1.64 V. The devices show a peak DC common-emitter current gain (β) ~ 20 and VBR,CEO = 2.5 V.

Abstract-We report an InPZIn0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz fτ and 800-GHz fmax. The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/μm2 with Jc = 18.4 mA/μm2 and Vce = 1.64 V. The devices show a peak DC common-emitter current gain (β) ~ 20 and VBR,CEO = 2.5 V.

We report an InP/In0.53Ga0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz f(tau) and 800-GHz f(max). The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/mu m(2) with J(c) = 18.4 mA/mu m(2) and V-ce = 1.64 V. The devices show a peak DC common-emitter current gain (beta) similar to 20 and V-BR,V- CEO = 2.5 V.

III-V FETs are in development for both THz and VLSI applications. In VLSI, high drive currents are sought at low gate drive voltages, while in THz circuits, high cutoff frequencies are required. In both cases, source and drain access resistivities must be decreased, and transconductance and drain current per unit gate width must be increased by reducing the gate dielectric thickness, reducing the inversion layer depth, and increasing the channel 2-DEG density of states. We here describe both nm self-aligned fabrication processes and channel designs to address these scaling limits.

We report a 110 nm InP/In0.53Gao.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating a simultaneous ft/fmax 465/660 GHz and operating at power densities in excess of 50 mW/μm2. To our knowledge this is the smallest junction width reported for a III-V DHBT. The narrow 110 nm emitter junction permits the devices to be biased simultaneously at high voltages and high current densities (Je) with peak RF performance at 41 mW/μm2 (Je = 23.6 mA/μm2, Vce = 1.75 V). Devices incorporate low contact resistance, refractory, in-situ Mo emitter contact to a highly doped, regrown InGaAs cap. A low stress, sputter deposited, refractory, dry-etched W/Tio.ιWo.9 emitter metal process was developed demonstrating both high emitter yield and scalability to sub-100 nm junctions. The emitter metal contacts reported here are 100 nm wide and the emitter-base junction width is 110 nm. On-wafer Through-Reflect-Line (TRL) calibration structures were used to measure the RF performance of devices from 140 -180 GHz.

The authors report ultralow specific contact resistivity (ρc) in ex situ Ohmic contacts to n-type In0.53Ga0.47As (100) layers, with an electron concentration of 5×1019 cm−3. They present the ρc obtained for molybdenum (Mo) contacts to n-type In0.53Ga0.47As, with the semiconductor surface cleaned by atomic H before metal deposition. The authors compare these data with the ρc obtained for contacts made without atomic H cleaning. After exposure to air during normal device processing, the semiconductor surface was prepared by UV-ozone exposure plus a dilute HCl etch and subsequently exposed to thermally cracked H. Mo contact metal was deposited in an electron beam evaporator without breaking vacuum after H cleaning. Transmission line model measurements showed a contact resistivity of (1.1±0.9)×10−8 Ω cm2 for the Mo/In0.53Ga0.47As interface. This ρc is equivalent to that obtained with in situ Mo contacts [ρc=(1.1±0.6)×10−8 Ω cm2]. Ex situ contacts prepared by UV-ozone exposure plus dilute HCl (without any atomic H exposure) result in ρc=(1.5±1.0)×10−8 Ω cm2.