We consider the present performance, design principles, and prospects for further improvement, in THz transistor technologies, addressing how transistor characteristics limit IC performance, and showing several 100-300 GHz IC and systems examples.

We report a two gain-stage 220-GHz solid-state power amplifier (SSPA) monolithic integrated circuit (MMIC)having high output power (P-out) and record power-added efficiency (PAE) exceeding 20% above 200-GHz operation. The transistor technology is 130-nm InP HBT. TheS21mid-bandgain is 13.9-dB. Typical return loss values for|S-11|and|S-22|exceed 6.3- and 12.7-dB, respectively. The dc power dissipation is 183-mW (P-dc). From 217.5- to 225-GHz, the saturated output power P-sat is 57-62-mW (1.78-1.93 W/mm RF power density)with 6.1-6.5 dB gain and 20%-23.8% PAE-peak values for P-out, gain, and PAE are at 220-GHz operation. The 1-dB gain compression P-out(OP1 dB) at 220-GHz is 31.6-mW with 15.9%PAE. The power amplifier is very compact, 0.192-mm2in size. This work represents the first solid-state power amplifier operating above 200-GHz having PAE greater than 20%. Compared to the previous state-of-the-art, PAE has been increased by1.36 times; however, when compared to 200-GHz PAs with similar output power, state-of-the-art PAE has instead been increased by2.3 times.

We report a three-stage power amplifier (PA), using 250-nm indium phosphide (InP) heterojunction bipolar transistors (HBTs), that achieves 18.4% peak power-added efficiency (PAE) with 18.8-dBm associated output power (P-out) and 13.8-dB associated power gain at 221.5 GHz. The amplifier has 19.5-dB peak S-21 and 212-238-GHz 3-dB bandwidth. The output stage combines the output power of four power transistor cells, each cell being a capacitively degenerated common-base stage with four parallel HBTs, each HBT having 5- $\mu\text{m}$ emitter length. Within each power transistor cell, separate base dc bias resistances for each emitter finger significantly increase the safe operation area (SOA), allowing dc bias at a greater collector current density at any given collector-emitter voltage. The increased SOA improves the amplifier P-out and power-added efficiency (PAE). The simulated loss of the 4:1 output power combiner is only 1 dB at 230 GHz. To the authors' knowledge, this is the highest published PAE for a transistor amplifier operating above 200 GHz.

We report two 220-GHz solid-state power amplifiers (PA, SSPA) having high output power (P-out) and record power-added-efficiency (PAE). The first amplifier (PA- 1) uses a 250-nm InP HBT technology. The S21 gain is 19.6-dB. DC power dissipation is 230-mW (PDC). From 215-225 GHz, the saturated output power Psat is 35.9-41.2 mW (1.12-1.29 W/mm RF power density) with 7.2-7.5 dB gain and peak 12.5-14.4% PAE. The 5-dB gain compression Pout (OP5dB) at 220-GHz is 29.7-mW with 12.4% PAE. PA size is 0.264-mm(2). The second amplifier (PA-2) uses a 130-nm InP HBT technology. The S21 gain is 14.8-dB. P-DC is 156-mW. From 217.5-225 GHz, P-sat is 45-50 mW (1.41-1.56 W/mm) with 6.2-7.2 dB gain and peak 25.0% PAE. The OP5(dB) at 220-GHz is 47.2-mW with 25.0% PAE. At an elevated HBT bias voltage, higher P-out is demonstrated but with small reductions to PAE. PA size is 0.192-mm(2). This work represents world-class, high-efficiency solid-state power from two InP HBT technology nodes, where record 25% PAE with 46-mW P-out is demonstrated at 220-GHz.

We report a five-gain-stage 150–175-GHz solid-state power amplifier (PA, SSPA) monolithic microwave integrated circuit (MMIC) having modest 20–21-dBm output power $P_{\mathrm {out}}$ , high gain, and high power-added efficiency (PAE). The transistor technology is 250-nm InP HBT. The $S_{21}$ gain is 31.4 ± 1.2 dB from 100 to 178 GHz. The 3-dB $S_{21}$ bandwidth is between 96 and 181 GHz. Typical return loss values for $\vert S_{11}\vert $ and $\vert S_{22}\vert $ exceed 8.5 and 10 dB, respectively. The dc power is 0.72 W. Across 150–175 GHz, the saturated output power $P_{\mathrm {sat}}$ is 106–126 mW with 16–18-dB gain and 12.5%–16.2% PAE—peak values for $P_{\mathrm {out}}$ , gain, and PAE are at 170-GHz operation. The 1-dB gain compression $P_{\mathrm {out}}$ (OP $_{\mathrm {1\,dB}}$ ) is 30–60 mW. Across the $D$ -band (110–170 GHz), $P_{\mathrm {sat}}$ is 82–126 mW with 9.1%–16.2% PAE. This work establishes a 1.62– $1.89\times $ increase to PAE over 150–175 GHz operation at the output power and gain levels cited. It is also the highest RF output power demonstrated across the full 110–170-GHz WR6.5 waveguide band.

High-efficiency power amplifiers (PAs) will be critical building-blocks for future sub-THz communications systems. InP heterojunction bipolar transistors (HBTs) with THz-class transistor bandwidth demonstrate PAs with high RF power density and high efficiency at frequencies between 100-300GHz. We review the performance of a state-of-the-art InP HBT IC technology and reported IC results that are applicable to future sub-THz communications systems.

We report a five-gain-stage 150–175 GHz solid-state power amplifier (PA, SSPA) integrated circuit (MMIC) having 23–24 dBm output power Pout, high gain, and high power-added-efficiency (PAE). The transistor technology is 250-nm InP HBT. The S21 gain is 31.7±1.7-dB from 97–171 GHz. The 3-dB S21 bandwidth is between 95–177 GHz. Return loss values for |S11| are 4.6-16.2 dB and for |S22| exceed 9.6-dB. DC power is 1.50-W. Across 150–175 GHz, the saturated output power Psat is 204–250 mW with 17-dB gain and 13.1-15.7% PAE - peak values for Pout and PAE are at 160-GHz operation. The 1-dB gain compression Pout (OP 1dB ) is 93–123 mW. Across D-band (110–170 GHz), Psat is 140–250 mW with 7.7-15.7% PAE. Compared to the previous state-of-the-art, this work matches the highest output power demonstrated at 150–175 GHz G-band operation but has established a new benchmark with a 1.9-2.2× increase to PAE.

We report a three-gain-stage 88-104-GHz W-band solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) having modest 100-140-mW output power (P-out), high gain, and high power-added efficiency (PAE). The MMIC technology is 250-nm InP HBT. PA S-21 gain is 29.5 dB with +/- 0.5-dB variation. PA 3-dB S-21 gain roll-off is between 88 and 104.5 GHz with high vertical bar S-11 vertical bar and vertical bar S-22 vertical bar return losses. DC power (P-dc) is 0.41 W. Across 88 -104 GHz, the PA-saturated output power Psat is 100-120 mW with greater than 20-dB power gain and 20% PAE. At 92 GHz, peak 120-mW P-out with 20-dB gain and 24.7% PAE is demonstrated. P-out at 1-dB gain compression OP1-dB is estimated to be 15-17 dBm. At 94 GHz and an elevated output stage bias (0.50-W P-dc), 140-mW P-out with 20-dB gain and 24.4% PAE is demonstrated. This work contributes to and improves the state of the art for W-band PAs in the simultaneous performance areas of power, gain, and PAE.

Two high-gain, high power-added-efficiency (PAE) G-band solid-state power amplifier (SSPA) MMICs operating between 160–183 GHz are reported. Both utilize an identical five-stage gain-lane, and on-chip combining of these gain-lanes satisfies the output power (Pout) objectives. The first result is a 0.24-W PA using 4-way power combining. S21 mid-band gain is 21.0 dB and DC power dissipation (P DC ) is 3.05-W. The 3-dB S21 bandwidth (BW) is between 158.5-182.8 GHz. At 170-GHz, peak Pout is 244-mW (7.5% PAE). Pout is no less than 0.20-W between 160–180 GHz and is 177-mW at 183-GHz. The 170-GHz OP 1dB 1-dB gain compression is 120-mW (3.8% PAE). This PA result improves upon the prior state-of-the-art by 2.2-2.8× for peak SSPA power. The second result is a 0.14-W PA using 2-way combining. S21 mid-band gain is 23.6 dB and P DC is 1.35-W. The 3-dB S21 BW is between 161.0-184.8 GHz. At 170-GHz, peak Pout is 140-mW (9.50% PAE), and Pout is 116–140 mW (8.0-9.5% PAE) between 160–183 GHz. The 170-GHz OP 1dB is 70-mW (5.1% PAE). This PA result improves upon the prior state-of-the-art by 1.4-1.6× for peak SSPA power. This work establishes new SSPA RF power, gain, and PAE performance benchmarks at 160–183 GHz operation using a 250-nm InP HBT technology.

We report a 250nm InP HBT MMIC that demonstrates record output power at 44 GHz for its chip size, having a small signal bandwidth of 25 - 50 GHz, and operating from a 2.5-2.8 V supply. The reported power amplifier delivers up to 185 mW and has a peak PAE of 38% at 44 GHz. The results in this work highlight the relevance of 250nm InP HBT devices for emerging size-constrained platforms including MIMO communication front-ends and radar applications.

Two high-gain, broadband power amplifier MMICs are reported. The first result is a 140-GHz 0.25-W PA. It utilizes 5-gain stages and 4-way power combining. S 21 gain is 29.4-dB. It demonstrates over 0.21-W P out across 110-150 GHz. 0.25-W P out at 140-GHz requires 4-dBm P in - the associated gain is 16-dB with 7.0% PAE. The 140-GHz OP 1dB 1-dB gain compression is 171-mW with 4.9% PAE. The 3-dB S 21 bandwidth (BW) is between 112-148 GHz. This result improves state-of-the-art by 65% at 140-GHz for peak SSPA power. The second PA result is a 55-135 GHz 115-135 mW PA. It utilizes 4-gain stages and 2-way power combining. Its operation fully covers WR15 (50-75 GHz) to WR08 (90-140 GHz) bands. S 21 gain is 27.3-dB. The S 21 fractional BW at 1-dB and 3-dB gain roll-off are 63% and 81%. Large-signal BW associated with high power and gain between 55-135 GHz is 84%. P out variation over this span at 3-dBm P in is only 11.2% (±13-mW). This result improves state-of-the-art for mm-wave PA's where simultaneously high P out , fractional BW, gain, and gain flatness are required.

In this paper we review the status of the state-of-the-art and our transition activities for mm-wave, D-, and G-band solid-state power amplifier (PA) MMICs developed into Teledyne Scientific's 250-nm InP HBT technology. Key design decisions driven by the transistor gain at a given frequency and large-signal load-line are reviewed. Novel PA cell topologies are presented to show how they address the high current biasing required of the 250-nm InP HBT and permit 2× and 4× on-chip combining. PA wafer-mapping by auto-probing on a full thickness 100-mm wafer prior to finishing (thinning to 3-mil, chip singulation) permits the RF identification of known-good-die (KGD) and thus an inventory of parts can be generated. Five established 250-nm InP HBT power amplifiers are presented operating from 55-135 GHz (115-135 mW), 60-130 GHz (160-275 mW), 115-145 GHz (0.25-W @ 140-GHz), 115-185 GHz (75-115 mW), and 180-250 GHz (40-80 mW). Also, included is a novel 190-GHz low-power driver amplifier (high-gain, 100-mW P DC , 3-dBm OP 1dB , 11-dBm P sat with 9.6% PAE).

We report here a 250-nm InP HBT based wideband power amplifier that operates between 110-190 GHz and fully covers D-band (110-170 GHz). It utilizes 5-gain stages and 2-way on-chip power combining. The amplifier demonstrates 25.2-dB S21 mid-band gain and 68-117 mW output power between 110-190 GHz. The fractional bandwidth associated with 1-dB and 3-dB S21 gain roll-off are 35% (54-GHz) and 43% (66.5-GHz), respectively. The fractional large-signal power bandwidth associated with highest power between 110-190 GHz is 53%. Under small, medium, and large-signal operation, the PA is most efficient between 115-185 GHz - at 3-dBm input power, 73-104 mW output power (5.0-7.5 % PAE) is demonstrated over this frequency span. This result represents a significant increase to the state-of-the-art for a mm-wave solid-state power amplifier operating across D-band and a significant fraction of G-band in the simultaneously demonstrated metrics of high output power (by 3-4x higher), bandwidth, gain, and gain flatness.

We report here a compact 140-GHz, 150-mW high-gain solid-state power amplifier (SSPA) monolithic microwave integrated circuit (MMIC) demonstrated in a 250-nm InP HBT technology. It utilizes five-gain stages and two-way on-chip power combining. The amplifier measures 29.5-dB mid-band $S_{21}$ gain and over 125-mW output power across 115–150-GHz operation. The peak 153-mW output power was measured at 140 GHz using only 2.7-mW RF input power—the associated large-signal gain is 17.5 dB with 9.8% power added efficiency (PAE). The 140-GHz OP1 dB 1-dB gain compression power is 106 mW with 7.0% PAE. The dc power dissipation is 1.54 W and its size is only 0.75 mm2. The 3-dB $S_{21}$ gain roll-off is between 112 and 147 GHz. The 115–150-GHz output power variation at 0-dBm input drive is only ±0.5 dB. The peak PAE varies between 8.2% and 10.5%. This D-band result improves upon by $2.3\times $ at 140 GHz the state-of-the-art peak RF power previously demonstrated by SSPA MMICs.

We report here two 250-nm InP HBT power amplifiers operating between 180-265 GHz. A 3-stage, 8-PA cell combined design demonstrates S21 gain exceeding 25-dB between 202-257 GHz and 20-dB between 194-265 GHz. Peak output power is 140-mW at 200-GHz with 14.7-dB gain and 5.1% PAE. The PA P sat RF power is at least 100-mW from 190-235 GHz, 82-mW from 183-245 GHz, and 50-mW from 183-263 GHz. This represents 80-GHz large-signal bandwidth from this design. A 3-stage, 16-PA cell combined design demonstrates S21 gain exceeding 24-dB between 200-255 GHz and 20-dB between 194-262 GHz. Peak output power is 248-mW at 200-GHz with 9.0-dB gain and 4.1% PAE. The PA P sat RF power is at least 200-mW from 195-215 GHz, 170-mW from 190-220 GHz, and 100-mW from 185-255 GHz. This represents 70-GHz large-signal bandwidth from this design. These InP HBT amplifier chips represent improvements to state-of-the-art in the following areas: 13% increase to the maximum PA power reported above 200-GHz, first reported 200-mW PA power with 20-GHz (195-215 GHz) operation, highest PA power reported above 240-GHz, first demonstrated 100-mW power to 255-GHz, and 70-GHz (16-cell PA) and 80-GHz (8-cell PA) bandwidth covering most of the WR04 waveguide frequency band.