Brain inspired in-memory computing using networks of analog non-volatile memory (NVM) elements has emerged as a promising, more energy efficient alternative to digital computing for data intensive applications [1] . Since information processing is performed in the analog domain, control of electrical noise in the NVM elements becomes critical for achieving optimum accuracy [2] [3] . Here, we compare the noise characteristics of two NVM device types with programming mechanisms that depend on ion motion: electrochemical random access memory (ECRAM) and filamentary resistive random access memory (ReRAM). [4] [5] [6] . Furthermore, we demonstrate that ECRAM with a VO 2 channel, a material that exhibits an insulator-to-metal transition (IMT), enables manipulation of the noise characteristics, which can be utilized for hardware implementation of Bayesian Neural Network [7] .
Analog in-memory computing with resistive memory devices is a compelling alternative to conventional digital von Neumann computers [1]. Recent advancements in learning algorithms and hardware optimizations have enabled the utilization of ReRAM technology for deep neural network training purposes [2], in addition to inference. Specifically, ReRAM devices based on Conductive-Metal-Oxide (CMO)/HfO x stacks exhibit lower programming stochasticity and finer conductance updates [3], [4]. The physical explanation of the enhanced device performance is still debated. Previous reports have attributed it to multiple filament switching [5], or to oxygen content modulation in the CMO region above a single filament [6]. To maximize the potential of this technology for both inference and training applications, a comprehensive understanding of the intrinsic sources of noise is required. Prior research on nanometer-scale devices has demonstrated noise properties being dependent on device resistance, frequency, and applied voltage [7], [8]. In particular, low-frequency noise measurements offer valuable insights into the electronic transport and noise-generating mechanisms. This study investigates read noise in CMO/HfO x ReRAM devices and compares it with other systems.
Dynamic random-access memory (DRAM) is popular as a main memory due to fast and reliable memory. DRAM has a simple architecture with only one transistor and one capacitor, making it low-power and highly integrated [1] . However, the DRAM cell faces some issues, such as current leakage at the nanoscale device level and the need for periodic refresh. To overcome these issues, researchers are looking into utilizing a floating body of single Silicon-on-Insulator (SOI) MOSFETs as charge storage [2] – [4] . The Capacitorless DRAM (1T DRAM) cell operations are based on charge (hole) generation and recombination [2] – [4] . Accumulation of holes in the floating body represents the state “1”, while evacuation of holes from the body is the state “0”. The difference between these states is termed the sensing margin ( SM ), and retention time ( T ret ) is evaluated at a time when the difference between these states reaches 50% of its maximum value [2] – [4] . In this work, we have proposed a new device design with an elongated storage region to improve the retention time of 1T DRAM cell at a shorter gate length and higher temperature.
Double spin torque magnetic tunnel junctions (dsMTJ) serve as advanced nonvolatile memory, impacting sectors like computing, automotive, and storage [1] . dsMTJs rely on a magnetic tunnel junction (MTJ) with a CoFeB reference (RL) and free layer (FL), separated by an MgO tunnel barrier (TB), improved with a second RL separated by a non-magnetic spacer (NMS). Yet, smaller devices face reliability issues, such as back-hopping from higher current densities, undermining memory stability [2] . Interlayer exchange coupling (IEC) is crucial for enhancing memory cell performance and stability in compact MTJ stacks, in order to achieve higher memory density and to overcome traditional architecture limitations, thereby boosting memory reliability and performance [3 , 4] .
Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) are pivotal for next-generation power switching applications due to their wide band gap, high current density, extensive operating temperature range, and high breakdown voltage [1] , [2] . The reliability and performance stability of GaN-HEMTs depend on the selection of the substrate and buffer layers influenced by the presence of defects and strain resulting from lattice mismatch. Thus, assessing device performance under various stimulations, such as bias and temperature acceleration, is essential to achieve reliable devices [3] . In this work, we examine the impact of PBTI on industry-standard power GaN MIS-HEMTs featuring two distinct buffer layers: AlN/AlGaN/GaN supper lattice (W1) and three steps graded AlGaN (W2), under positive-biased stress at V GS =20 V. PBTI tests reveal that W2 induced less Vth instability compared to W1 during positive bias stress. However, W1 demonstrates a faster recovery rate than W2, showing its superior robustness and more suitability for power switching applications.
Over the last 60 years, the continuous miniaturization of transistors has allowed for enhanced density and functionality on the chip and significant improvements in switching speeds. However, scaling the supply voltage in the standard field effect transistors (FETs) is limited by the fundamental physical limit posed by the thermionic injection of the carriers (SS ≥60 mV/decade at room temperature). This increases the leakage current and the power dissipation. Tunnel FETs (TFETs) operating on the band-to-band tunneling mechanism were proposed to overcome the limit. They produce steep subthreshold characteristics but usually suffer from low ON-state currents [1] . 2-D materials have shown great potential for next-generation electronic devices due to their atomic-scale thickness (smaller tunneling distance and, consequently, relatively high ON currents), dangling bond-free interfaces, and suitable bandgaps [2] . Here, we explore the intrinsic performance of the devices composed of monolayer ZrI 2 , a potential 2-D semiconductor for next-generation electronic devices [3] , from first principle calculations. We propose the enhancement of the device performance by combining the desirable SS characteristics of TFETs with the ON-state characteristics of double gate (DG) FETs to obtain a device with a steep SS and a promising ON current [4 , 5] .
Gallium nitride (GaN) Super-Heterojunction FET (SHJ-FET) utilizes a charge-balanced PN heterojunction, instead of a field-plate structure, to manage the E-field profile between the gate and the drain [1] . GaN SHJ-MOSFETs with a blocking voltage of 10 kV and an R DS,ON C O (tr) figure-of-merit of approximately 4.9 ps have been reported, indicating potential for efficient and fast switching medium voltage power electronics [2] . It relies on a source-connected p-GaN contact to enable hole injection and depletion during switching. One concern about the prospect of the SHJ FET is that the switching time could be limited by the low doping efficiency and low hole mobility in the P-GaN. Previous work [3] revealed that the turn-on time has a quadratic dependence on the SHJ length, reaching μs-range for 10-kV-class device designs. For lower-voltage applications, e.g. 48V-1V point-of-load DC-DC converters, the SHJ length will be scaled down substantially from ~80 μm to 3 μm or less. Contact resistance to the p-GaN is expected to play a more important role in the switching time [4] . Through physics-based and mixed-mode TCAD simulations, this paper reveals the impact of p-GaN ohmic contact resistivity on switching time.
We present a comprehensive performance comparison of P-on-N and N-on-P Si-avalanche photodiodes (APD). We use our in-house experimental results of P-on-N APDs to calibrate the simulation framework for direct-current (DC) current-voltage (IV) characteristics and DC linearity study of the device under excess illumination. Using the calibrated setup, we simulate the N-on-P APD and show a 3× higher responsivity at 450 nm and a substantial increase in the responsivity at 801 nm illumination compared to P-on-N APD. We show that this reordering of the doping stack does not affect the response time and breakdown characteristics of the APD, which makes the N-on-P APDs an undisputed choice for low-photon count detection and imaging applications over P-on-N APDs.
The rapid evolution of artificial intelligence technologies has escalated the need for compact, high-density memory solutions [1] . Monolayer hexagonal boron nitride resistive random access memory (ML hBN RRAM) emerges as a particularly promising candidate due to its simple, ultra-thin metal-insulator-metal structure. However, these atomristor devices usually wear out quickly, with a maximum of 100 DC linear sweeps reported in existing studies [2] . Our research has led to a groundbreaking enhancement: by integrating a conductive oxidized metal top electrode into monolayer hBN RRAM, we have significantly extended its durability, achieving over 2000 cycles at low operational voltages below 0.5 V. These devices also have demonstrated the ability to endure up to continuous 400 cycles under μs pulse voltage, and even more pulse cycles by reactivating them by DC sweeps. This is the first time monolayer 2D material RRAM has exhibited such a high number of DC cycles and shows the potential for higher pulse-operated endurance and future energy-efficient computing applications.
Bidirectional switches (BSW) are extensively employed in power applications, particularly in AC-AC matrix converters and solid-state circuit breakers. They facilitate current flow and voltage blocking in both directions symmetrically. Conventional BSWs without monolithic integration comprise discrete power transistors with anti-parallel freewheeling diodes, which results in additional parasitic effects and a large chip area [1] . Wide bandgap semiconductors including Silicon Carbide (SiC) and Gallium Nitride (GaN) have been investigated for building monolithic-integrated BSWs. Particularly, GaN-based monolithic BSWs using High Electron Mobility Transistors (HEMTs) with dual gates have been developed with a shared active region [2] . Owing to the two-dimensional electron gas (2DEG), GaN HEMTs perform reverse conduction in the absence of a body diode [3] . Vertical power device topologies are preferred over lateral counterparts by reducing on-resistance at a given breakdown rating [4] , and thus bidirectional vertical devices have drawn great interest. Monolithic BSWs based on SiC vertical transistors have been studied [5 , 6] , but to the best of our knowledge, no reports exist on GaN vertical devices. GaN Current Aperture Vertical Electron Transistors (CAVETs) are favorable for MHz high-frequency switching due to high carrier mobility [4] , showing a potential to outperform SiC MOSFETs with lower losses by simulation [7] . We demonstrated a monolithic BSW using GaN CAVETs for the first time, and the reverse conduction of CAVETs was investigated.
Silicon field emitter arrays (FEAs) -based cold cathodes have shown promise in many applications under harsh environments such as x-ray sources and high-power microwave devices due to the temperature independence of tunneling current and the property of ballistic transport [ 1 – 3 ] . We report an unexpected, yet reproducible Negative Differential Resistance (NDR) region within the device output characteristics of gated FEAs. These results were obtained by utilizing an on-chip flat silicon anode with etched stand-offs to define the anode-to-emitter distances of <100μm. Our analysis using calculations and simulation reveal that the parallel-plate configuration introduces a deceleration of electrons in the channel between the anode and gate when the anode voltage, V AE , is lower than the gate voltage, V GE .
Emerging two-dimensional (2D) materials and their van der Waals (vdW) heterojunctions are promising for high-performance optoelectronics devices [1] . In this work, we exploited polymorphic nature of 2D MoTe 2 , including 2H semiconductor and 1T’ semimetal phases, integrated with low-energy vdW contacts to demonstrate novel and superior photoresponse in both phototransistor and photodiode configurations. Especially, 2H-MoTe 2 has intrinsic ambipolar charge transport with an inherent n-type photogating effect, giving rise to a reconfigurable photodetection. This work presents the potential of 2D MoTe 2 for future high-performance multi-functional optoelectronics.
The rapid evolution of quantum computing drives the demand for CMOS cryogenic electronics to support qubit scaling ( Fig. 1 ). In this regard, we present a 16 nm FinFET technology-based cryogenic low noise amplifier (LNA) crucial for enhancing qubit readout fidelity [1] . FinFETs offer fewer temperature deviations compared to planar generations due to improved gate control [ 2 – 3 ] . The choice of the 16 nm technology node maximizes modern digital capabilities and enables superior system-on-chip (SoC) integration for quantum applications. Our circuit design is based on the cryogenic FinFET device gain and noise temperature characterization at 20 K ( Fig. 2 ) with 50-Ohm ports and the given device models down to −40°C ( Fig. 3 ). Although transistor operation at low temperatures follows standard theory, deviations occur due to factors such as dopant freeze-out and subthreshold slope saturation caused by band tails [4] . This underscores the need for accurate device characterization at low temperatures during the early design stages. Initial results at 4 K suggest the FinFET LNA's potential for low noise, low power, and high gain operation.
Continuous technological scaling of static random-access memory (SRAM) has produced chips that are smaller, faster, and more energy-efficient. SRAM is a volatile memory and its data remanence refers to the persistence of data after the chip is powered down. As SRAM memory is prevalent in CPU cache and embedded systems, it frequently stores critical information such as cryptographic keys, passwords, and other confidential data. Consequently, a data remanence-based attack on SRAM can result in significant damage. Previous studies [1] , [2] suggest that data does not disappear immediately upon power-off but persists for a duration ranging from microseconds to seconds, depending on the SRAM sample. Therefore, a fundamental understanding of the data remanence of commercial SRAM memory is crucial for the security assessment of SRAM-based computing systems.
Vector-Matrix-Multiplication (VMM) via multiply and accumulate operation (MAC) is essential in computations encompassing neuromorphic and deep learning applications ( Fig. 1a ) [1] . The research has been focused on emerging non-volatile memories (NVMs) with resistive random-access memories (RRAM) as a leading candidate for a viable alternate technology [2] . In crossbar arrays, the currents through the columns/bit lines follow KCL and Ohm’s law, resulting in MAC, thereby reducing computational complexity ( Fig. 1b ) [3] . However, given the device’s non-idealities, it poses challenges in achieving accuracy levels. The accumulated current collected at the bit line is susceptible to bit-cell variability (I var ), a finite current ratio (k) , and the current contribution from the “off” state (high resistance state- I HRS ) ( Fig. 1c ) [4] . This work emphasizes the importance of a device-aware quantization scheme, i.e., considering device non-idealities at MAC outputs. We analyze the contribution of different non-idealities in defining the quantization scheme using Pr 1-x Ca x MnO 3 (PCMO) based RRAM arrays. Using non-uniform quantization, we show a successful VMM via MAC operation in PCMO-RRAM arrays. Further, we show how non-uniform quantization for non-ideal current can facilitate (2x) the size of the array compared to uniform quantization. While non-uniform quantization allows for a larger array, the constraints by tolerable device variability can be stringent and limit the array size. For an array size (n) of 4 and a current ratio (k) of 5, the estimated tolerable I var is less than 0.2I HRS .
GaN complementary transistors (CT) are highly desirable for GaN integrated circuits with low static power dissipation [1] . While recent experiments studied the feasibility of GaN CT [2 , 3] and improved GaN p-channel field effect transistor (p-FET) [4 , 5] , further advancements, e.g. in high temperature (HT) operation, would fully realize the potential of this emerging technology. HT operation (> 300°C, beyond the Si CMOS limit) is necessary to ensure its reliability at high power, harsh environment applications, and reduced thermal management needs. The degradation of electrode metal and gate dielectric was found to be the main challenge of GaN devices for HT operation [6 , 7] .
Amorphous oxide semiconductors like indium tin oxide (ITO) have attracted attention because their low-temperature deposition is compatible with back-end-of-line integration [ 1 – 3 ] . However, the stability of such oxide field-effect transistors (FETs) remains one of the primary challenges in their implementation. Recent studies have explored their threshold voltage ( V T ) stability under positive bias stress [ 4 – 6 ] , but the effect on parameters like field-effect mobility ( μ FE ) is seldom investigated. Here, we study top-gated indium tin oxide (ITO) FETs under positive bias stress, comparing devices with different V T achieved by O 2 engineering. We monitor the change in both V T and μ FE , as we perform stress measurements at room temperature (RT) and 85 °C. We achieve median |Δ V T | ≤ 60 mV at RT for all μ FE ≈ 5, 17, 23, and 37 cm 2 V −1 s −1 , with |Δ V T | increasing to ~50, 200, 460, and 390 mV at 85 °C respectively. We also explore the stress effect on μ FE for the first time in oxide FETs, observing up to 3× change in μ FE (from ~4.4 to 13.5 cm 2 V −1 s −1 ) upon stressing at RT.
Achieving a universal memory capable of delivering non-volatility with high speed and energy-efficient operation has been the primary motivation in memory research. ULTRARAM is an emerging compound semiconductor-based nonvolatile memory that exhibits degradation-free high endurance (>10 7 P/E cycles), retention (>1000 years), and ultralow switching energy per unit area (1000 times lower than flash). This paper presents a SPICE model of the ULTRARAM memory device for circuit simulations. The model includes the capture and release of the charges in the floating gate of the device utilizing TBRT physics and has been validated with experimental data.
Large-area electronic (LAE) thin-film transistors (TFTs) with GHz operation frequencies have enabled LAE-based wireless systems [1] . This motivates accurate modeling of GHz TFTs, but existing approaches are limited for two reasons [2] , [3] : (1) analytical models with numerous parameters are impractical for simulating complex circuits and systems; (2) important losses in the GHz regime are overlooked. Therefore, a non-quasi-static small-signal model has been proposed for GHz zinc-oxide (ZnO) TFTs [1] . However, to match measurements, this model requires an unrealistic value for gate resistance R G , which is a key frequency-limiting factor. Here we present an accurate and compact small-signal TFT model that includes losses from channel resistance, which are shown to be critical to GHz TFT performance. With physically realistic parameter values, this approach can precisely model GHz ZnO TFTs in both linear and saturation regimes. The model illuminates that reducing channel resistance losses is the key to raising the TFT’s operation frequency.
Backside power delivery with buried power rail (BPR) is one of the enabling technologies for 2 nm node and beyond [1] . Moving one step further, we believe that integrating active components in the backside of silicon, e.g., integrated voltage regulator (IVR), could provide further improvement in power conversion efficiency by minimizing the IR drop at the package/interposer level [2] . To minimize the power delivery loss, it is advantageous to place the IVR close to the voltage source (e.g., 12 V from the package/interposer) and perform voltage down conversion near the point of loads. However, most of the reported monolithic IVRs so far are placed at the frontside of silicon. One of the core elements in IVR is the flying capacitor. Unfortunately, today’s on-chip back-end-of-line (BEOL) compatible metal-insulator-metal (MIM) capacitor is mostly designed for handling voltage of <3.3 V. In this regard, it is timely to explore new capacitor technology featuring (1) backside of Si integration, (2) high breakdown voltage (> 6 V) (3) sufficient reliability (>10 yrs @ 85 °C) and (4) high 2D capacitance density (> 28 fF/μm 2 ) to pave the pathway for “active” backside power delivery to deliver >1 W/mm 2 power density. To the best of our knowledge, we report the first experimental demonstration of a Hf 0.25 Zr 0.75 O 2 /Al 2 O 3 laminate-based superlattice capacitor serving as the flying capacitor in a 12V-to-6V IVR. The stack is optimized to achieve the core requirements (1)–(3), and extensive reliability characterizations are performed for the lifetime projection based on the conduction mechanism.
