In this work, a procedure to obtain two-port admittance models of buried cables illuminated by incident electromagnetic fields for the analysis of transients in the frequency domain is presented. The procedure is based on cascading two-port admittance models of various cable segments, avoiding the numerical problems that chain matrix representations may have. To obtain results in the time domain, the Numerical Laplace Transform method is used.

In this article I ( Figure 1 ) interview four exceptional female engineering students in Mexico, one studying her MS in microwave engineering at The Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV) and three undergraduate students studying electronic engineering at ITESO - The Jesuit University of Guadalajara, all of whom want to pursue a career in microwave engineering.

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.

An optimization methodology to determine the best values of the compensation elements of a buck voltage regulator (VR) as well as the optimal number of decoupling capacitors in a power delivery network (PDN) application is proposed. A state average equivalent circuit model of the buck converter is employed. The proposed optimization methodology gradually finds the best compensation parameter values of a buck converter VR to meet some stability criteria in a PDN application. Additionally, the number of parallel decoupling capacitors in the PDN is minimized to simultaneously meet a frequency-domain impedance profile specification and a time-domain voltage droop requirement.

The design process of power delivery networks (PDN) in modern computer platforms is becoming more relevant and complex due to its relationship with high-frequency effects on signal integrity. When circuits start operating, the changing current flowing through the PDN produces fluctuations creating voltage noise. Unsuccessful noise control can compromise data integrity. A suitable PDN design approach is the use of decoupling capacitors to lower the impedance profile and mitigate current surges, ensuring a small variation in the power supply voltage under significant transient current loads. An optimization approach to determine the number of decoupling capacitors in a PDN is presented in this paper, aiming at decreasing the amount of decoupling capacitors without violating the PDN design specifications, looking at both the impedance profile in the frequency domain and the resulting voltage droop in the transient time-domain.

A methodology is defined to select the variables with the greatest impact on the response of the system to be used in the design of single-ended low speed interconnects. A point-to-point topology was studied in this work, consisting of a master and a slave buffer, package, and two transmission lines with a series resistor on the PCB. The considered response for the system was the flight time of digital signals coming out of the buffers. To lessen computational resources during optimization processes, surrogate models were obtained using design of experiments. To choose the active factors for the response, screening experiments were done. Then, to build the surrogate model face-centered and rotatable central composite designs for both the master and slave signals were compared in terms of model fit, with a 15% maximum error. The surrogate models were used to represent a Serial Peripheral Interface, which is a synchronous bus, and requires a timing analysis to assess the maximum allowed length of the routing. A Nelder-Mead algorithm with penalty functions was used to optimize the transmission lines lengths, while maintaining the timing margins equal to or larger than zero. Optimal lengths were validated using SPICE. The methodology proposed in this work can help in reducing design times for single-ended low-speed singles, as there would not be need to simulate the whole topology each time the value of a component needs to be changed.