Numerical circuit parameter extraction (PE) is a key sub-process of space mapping (SM), which is used to efficiently optimize full-wave EM responses of microwave structures exploiting faster but inaccurate physics-based auxiliary models. Any improvement in PE has a positive impact on SM design optimization. In this paper, we apply for the first time a PE formulation based on the Kullback-Leibler distance to microstrip filters using their full-wave EM responses as targets. We perform a rigorous numerical comparison of PE based on the K-L formulation against PE using classical norms. Our results confirm a better PE performance using the Kullback-Leibler formulation than those obtained with traditional PE formulations.

Space mapping (SM) techniques are commonly used for optimizing highly accurate models that require a large computational effort, known as fine models, by exploiting simplified physics-based models that are computationally fast but not accurate enough, known as coarse models. Most SM formulations require solving a parameter extraction (PE) subproblem at each iteration. Typically, SM algorithms use classical lth norms for the PE objective function. In this article, we first apply a PE formulation based on the Kullback-Leibler (K-L) distance to microstrip filters using their full-wave electromagnetic (EM) responses as targets, performing a rigorous numerical comparison against PE using classical norms. We subsequently propose, for the first time, a Broyden-based input SM algorithm using the K-L distance as objective function for the PE subproblem. We apply SM design optimization to several examples, beginning with a classical synthetic test example and following with some microstrip filters using their full-wave EM representation as fine models, and their equivalent distributed circuit as coarse models. A rigorous numerical comparison is also performed between classical lth norms and the K-L formulation for PE within the corresponding SM design optimizations. Our results indicate that SM with PE using the K-L formulation outperforms that one obtained by using the classical lth norm PE formulations within SM.

Semiconductor technology advances, coupled with the demand for higher data rates and bandwidth, has led to significant signal integrity issues such as attenuation, crosstalk, jitter, noise, EM susceptibility, etc. Traditional post-silicon validation methods for high-performance computer platforms, which rely heavily on manual inspection and rule-based heuristics, are increasingly inadequate for addressing these complexities. In this paper, we review and highlight the application of artificial intelligence (AI) approaches and machine learning (ML) techniques to automate post-silicon validation and enhance the detection and diagnosis of signal integrity issues in high-speed computer interfaces. Through a series of case studies, we demonstrate the efficacy of various AI techniques, including artificial neural networks (ANNs), surrogate modeling, and unsupervised learning, in optimizing settings and improving the efficiency of post-silicon validation. These techniques significantly reduce the number of required measurements, enhance accuracy, and provide scalable and flexible solutions for modern post-silicon physical layer validation and tuning processes.

The evolution of PCI Express technology to Gen6, and the forthcoming Gen7, has markedly increased data transfer speeds, presenting new challenges for signal integrity. To tackle these challenges, advanced design strategies, such as enhanced equalization (EQ) techniques, are necessary. Traditional EQ methods typically involve extensive laboratory measurements, rendering the EQ process highly time intensive. In this paper, we introduce an optimization methodology for the PCIe Gen6 transmitter (Tx) equalizer utilizing the Aggressive Space Mapping (ASM) algorithm. Our ASM approach employs a computationally efficient surrogate as coarse model to estimate eye diagram margins. An implicit mapping between the coarse and fine model equalizer settings is established, leading to an efficient optimization for the EQ tuning process. The effectiveness of the ASM methodology is confirmed through simulations with the MATLAB SerDes Toolbox, resulting in notable enhancements in the eye diagram area and overall system margins.

Differential interconnects are widely used for high-speed serial data transmission in modern high-performance computer platforms. Differential signaling handle noise better than single ended signaling. However, physical asymmetries and discontinuities in differential links can cause that a portion of the differential energy is converted into common mode (CM) energy, which is perceived as noise at the receiver. This mode conversion in differential interconnects leads to electromagnetic (EM) interference and EM susceptibility, limiting high data rates. In this paper, a microstrip differential interconnect with a severe discontinuity, a right-angle bend, is optimally compensated by using two rectangular length-match bumps. Our formulation allows the efficient optimization of the full set of mixed-mode (MM) S-parameters of the differential interconnect. It uses a smart combination of pattern search and Nelder-Mead to optimize the MM performance considering several starting points. The interconnect MM performance before and after optimization is shown, confirming a very significant performance improvement.

Parameter extraction (PE) is a key subproblem of space mapping (SM) design optimization. It consists of a local alignment between the coarse and fine models at each SM iteration. In this work, cognition-driven PE is proposed for SM. In contrast to classical PE, where the full fine model responses are used as targets, the proposed cognitive PE focuses on key features of the fine model response selected from an engineering perspective. It is demonstrated that the proposed cognitive PE approach: 1) yields more accurate extracted parameters regardless of the type of PE objective function employed; and 2) achieves a more meaningful matching to the fine model target response and with less variability. To proof this with independence of the optimization method employed for PE, plots of the PE objective functions are presented over large regions of the coarse model design space. Two synthetic examples are used to support these findings.

Cognition-driven design of RF and microwave circuits is an emerging and promising approach to efficient design optimization of computationally expensive fine models. Existing techniques for cognition-driven design have been developed for optimizing microwave filters without exploiting traditional coarse model representations, e.g., equivalent circuits. Instead, intermediate feature-space parameters have been used to establish other types of mappings in the design process. In this letter, a cognitive space mapping (SM) technique that fully exploits traditional coarse models is proposed for the first time. The proposed cognitive SM approach exploits a previous cognition-driven parameter extraction (PE) formulation at each SM iteration. This cognitive SM technique follows an algorithmic structure that is an extension of that one used by the Broyden-based input SM, better known as aggressive SM (ASM). A synthetic benchmark example illustrates the performance improvement of the proposed cognitive SM versus ASM.

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The fifth edition of LAMC will take place in San Juan, Puerto Rico, on January 22

In this article, we honor Prof. John W. Bandler and his legacy in RF and microwave modeling and automated design optimization. We showcase his pioneering breakthroughs in minimax optimization, p th norm formulations, yield optimization, and nonlinear circuit design optimization. We highlight advances in direct electromagnetic (EM) microwave optimization, circuit response sensitivities, and efficient S -parameters sensitivity calculations. We explore the port-tuning version of space mapping (SM) for EM-based analysis, techniques for industrial microwave design of satellite systems, and post-manufacture hardware tuning. The integration of artificial neural networks (ANNs) with SM for enhanced EM-based design optimization and yield prediction, cognition-driven microwave filter design, and parallels between SM and artificial intelligence (AI) is examined. Finally, we speculate on the future integration of cognitive science with engineering design, leveraging the synergy of AI, machine learning (ML), and SM.

We present, in this article, an up-to-date general and brief scan of the main research activities in RF and microwaves in Latin America. First, we geographically identify the main research and development clusters in RF and microwaves in this large region of the world. We next describe the most recent and representative research work developed in the most active Latin American countries in this technical field, namely, Argentina, Brazil, Chile, Colombia, Costa Rica, Ecuador, Mexico, Peru, and Puerto Rico. To develop this updated survey of RF and microwaves in Latin America, we started by considering previous similar reviews available in the literature [1] , [2] , including some focused on specific Latin American countries [3] , [4] . In our review, we essentially focus on the past five or six years of scientific research production. Given the synergistic relationship between the IEEE Microwave Theory and Technology Society (MTT-S) and the level of activities and maturity in RF and microwaves, we finalize our article by summarizing the status as well as the main challenges and opportunities for the MTT-S in Latin America.

Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry. The continuously increasing bandwidth demand from new applications has led to the development of the PCIe Gen5, reaching data rates of 32 GT/s. To mitigate undesired channel effects due to such high-speed, the PCIe specification defines an equalization process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding an optimal subset of Tx and Rx coefficients by measuring the eye diagrams across different channels. However, these experiments are very time consuming since they require massive lab measurements. In this paper, we use a K-means approach to cluster all available post-silicon data from different channels and feed those clusters to a Gaussian process regression (GPR)-based metamodel for each channel. We then perform a surrogate-based optimization to obtain the optimal tuning settings for the specific channels. Our methodology is validated by measurements of the functional eye diagram of an industrial computer platform.

The fourth edition of LAMC will take place in San Jose, Costa Rica, on December 6-8, 2023.After three successful editions in Puerto Vallarta, Mexico (2016), Arequipa, Peru (2018), and Cali, Colombia (2021, virtual), LAMC returns fully presential to San Jose as a high-quality technical forum for the Latin America Region and all the MTT-S community.San Jose, located in the central region of Costa Rica, is a strategic place nearby SJO International Airport, where principal government institutions, universities, and industry converge in a metropolitan area with over three million people.The west of this urban area hosts a vibrant business environment, with the operation of more than 300 high-tech companies in fields such as semiconductors, electronics, software, and biomedical applications, among others.

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The continuously increasing bandwidth demand from new applications has led to the development of the new peripheral component interconnect express (PCIe) Gen6, reaching data rates of 64 giga-transfers per second (GT/s) and adopting the pulse amplitude modulation 4-level (PAM4) signaling scheme. While PAM4 solves the bandwidth requirements, it brings new challenges for the physical channel design. PAM4 is more susceptible to errors due to various noise sources caused by reduced voltage (and timing) ranges, yielding a higher bit error rate (BER). It also introduces new challenges in slicers, transition jitter, and equalizers, making of equalization (EQ) a critical process for PAM4 signaling. In this paper, we propose a multi-stage continuous-time linear equalizer (CTLE) with high-band, mid-band, and low-band frequency boost stages to deal with highly lossy channels. Given the complexity of EQ of multi-level signals, optimization techniques are used, including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning.

Ever faster applications triggered the development of the new PCIe Gen6 specification, reaching 64 GT/s data rates with PAM4 modulation. This brings new challenges for the physical channel design, where equalization (EQ) plays a key role. PCIe specification defines an EQ process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding optimal subsets of Tx and Rx coefficients by measuring the eye diagram at the Rx across many different channels. However, these practices are very time consuming since they require massive lab measurements. In this paper, we propose machine learning techniques to cluster post-silicon data from different channels and feed those clusters to Gaussian process regression (GPR) models. We then optimize each GPR surrogate to obtain the optimal tuning settings for each identified cluster. Our methodology is validated by using MATLAB SerDes Toolbox simulations of the functional eye diagram of a Gen6 link.

This paper outlines the early history of optimization technology for the design of microwave circuits-a personal journey filled with aspirations, academic contributions, and commercial innovations.Microwave engineers have evolved from being consumers of mathematical optimization algorithms to originators of exciting concepts and technologies that have spread far beyond the boundaries of microwaves.From the early days of simple direct search algorithms based on heuristic methods through gradient-based electromagnetic optimization to space mapping technology we arrive at today's surrogate methodologies.Our path finally connects to today's multi-physics, system-level, and measurement-based optimization challenges exploiting confined and feature-based surrogates, cognition-driven space mapping, Bayesian approaches, and more.Our story recognizes visionaries such as William J. Getsinger of the 1960s and Robert Pucel of the 1980s, and highlights a seminal decades-long collaboration with mathematician Kaj Madsen.We address not only academic contributions that provide proof of concept, but also indicate early formative milestones in the development of commercially competitive software specifically featuring optimization technology.

Space mapping arose from the need to implement fast and accurate design optimization of microwave structures using full-wave EM simulators. Space mapping optimization later proved effective in disciplines well beyond RF and microwave engineering. The underlying coarse and fine models of the optimized structures have been implemented using a variety of EDA tools. More recently., measurement-based physical platforms have also been employed as “fine models.” Most space-mapping-based optimization cases have been demonstrated at the device-, component-, or circuit-level. However, the application of space mapping to high-fidelity system-level design optimization is just emerging. Optimizing highly accurate systems based on physical measurements is particularly challenging, since they are typically subject to statistical fluctuations and varying operating or environmental conditions. Here, we illustrate emerging demonstrations of space mapping system-level measurement-based design optimization in the area of signal integrity for high-speed computer platforms. Other measurement-based space mapping cases are also considered. Unresolved challenges are highlighted and potential general solutions are ventured.

Suboptimal design of power delivery networks (PDNs) may cause performance deterioration and severe functional failures on high-speed computer platforms. Voltage regulators (VRs) distribute controlled voltage in the PDN to the active devices, providing a steady power supply at a desired DC voltage level with an acceptable noise level or ripple. Unacceptable voltage drops can be caused by transient switching currents at the devices. Many decoupling capacitors are commonly used to lower the PDN impedance profile in order to reduce power supply noise and to supply fast transient current to switching devices. However, commercially available decoupling capacitors typically present large manufacturing variability. In this article, we first propose an optimization methodology that gradually finds the best compensation parameter values of a buck converter VR to meet suitable stability criteria. Simultaneously, the number of parallel decoupling capacitors in the PDN is minimized while meeting a frequency-domain impedance profile specification and a time-domain minimum voltage droop requirement under nominal parameter values. Finally, a statistical analysis, yield estimation, and yield optimization of the nominally optimized PDN subject to large decoupling capacitor tolerances is presented. We consider the impedance profile, transient voltage droop, and VR stability as the responses of interest for yield calculation.