We present BAG $3{++}$ , an extensible analog/mixed-signal (AMS) design framework for layout-aware design. BAG $3{++}$ realizes a unified design environment that merges schematic, layout, and verification views into a single development interface. We further introduce new automated design features that enable rapid automation and optimization across a range of performance specifications, processes, and applications. We demonstrate the practical use of these features through (a) a bit-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC) implemented in the open-source Skywater 130nm process and (b) an ultra-high speed output driver optimized in two modern processes. BAG $3{++}$ interfaces with both commercial and open-source design frameworks, and the extensibility of BAG $3{++}$ is further illustrated through the integration of an open-source simulator.

We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

This paper presents an adaptive encoding framework for the reduction of coupling transition activity in on-chip data buses. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster with bit-lines. The proposed method utilizes redundancy in space and time to prevent loss of information while retrieving data. Unlike off-chip buses, the focus is to decrease coupling transitions which consume higher power than switching transitions in this scenario. We present analytical and experimental results which demonstrate the activity reduction of our encoding scheme for various data sets.

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (ΔΣ) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under ~6dB channel loss at 50GHz.

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process.

The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture.

This work presents a 16mm2 heterogeneous RISC-V system-on-a-chip (SoC) composed of a high-performance out-of-order core, energy-efficient in-order core, data-parallel vector accelerator, and systolic array deep neural network (DNN) accelerator in low-power Intel 22FFL for general-purpose compute, DNN, and vector workloads. The heterogeneous RISC-V SoC is composed of fully open-source components, including a second-generation Berkeley Out-of-Order Machine (BOOM) with a non-speculative mode attached to a Hwacha vector accelerator, a Rocket in-order core attached to a Gemmini systolic array DNN accelerator, as well as a IMiB L2 cache and off-chip I/Os. Combined, the variety of heterogeneous compute allows for wide programmability while providing up to a 286x MOPS/W improvement or 282x MOPS improvement over the RISC-V in-order core.

Neuromorphic computing, inspired by the brain, promises extreme efficiency for certain classes of learning tasks, such as classification and pattern recognition. The performance and power consumption of neuromorphic computing depend heavily on the choice of the neuron architecture. Digital neurons (Dig-N) are conventionally known to be accurate and efficient at high speed while suffering from high leakage currents from a large number of transistors in a large design. On the other hand, analog/mixed-signal neurons (MS-Ns) are prone to noise, variability, and mismatch but can lead to extremely lowpower designs. In this paper, we will analyze, compare, and contrast existing neuron architectures with a proposed MS-N in terms of performance, power, and noise, thereby demonstrating the applicability of the proposed MS-N for achieving extreme energy efficiency (femtojoule/multiply and accumulate or less). The proposed MS-N is implemented in 65-nm CMOS technology and exhibits > 100x better energy efficiency across all frequencies over two traditional Dig-Ns synthesized in the same technology node. We also demonstrate that the inherent error resiliency of a fully connected or even convolutional neural network can handle the noise as well as the manufacturing nonidealities of the MS-N up to certain degrees. Notably, a system-level implementation on CIFAR-10 data set exhibits a worst case increase in classification error by 2.1% when the integrated noise power in the bandwidth is similar to 0.1 mu V2, along with +/- 3 sigma amount of variation and mismatch introduced in the transistor parameters for the proposed neuron with 8-bit precision.

Neuromorphic computing, inspired by the brain, promises extreme efficiency for certain classes of learning tasks, such as classification and pattern recognition. The performance and power consumption of neuromorphic computing depends heavily on the choice of the neuron architecture. Digital neurons (Dig-N) are conventionally known to be accurate and efficient at high speed, while suffering from high leakage currents from a large number of transistors in a large design. On the other hand, analog/mixed-signal neurons are prone to noise, variability and mismatch, but can lead to extremely low-power designs. In this work, we will analyze, compare and contrast existing neuron architectures with a proposed mixed-signal neuron (MS-N) in terms of performance, power and noise, thereby demonstrating the applicability of the proposed mixed-signal neuron for achieving extreme energy-efficiency in neuromorphic computing. The proposed MS-N is implemented in 65 nm CMOS technology and exhibits > 100X better energy-efficiency across all frequencies over two traditional digital neurons synthesized in the same technology node. We also demonstrate that the inherent error-resiliency of a fully connected or even convolutional neural network (CNN) can handle the noise as well as the manufacturing non-idealities of the MS-N up to certain degrees. Notably, a system-level implementation on MNIST datasets exhibits a worst-case increase in classification error by 2.1 is 0.1 uV2, along with +-3σ amount of variation and mismatch introduced in the transistor parameters for the proposed neuron with 8-bit precision.

This paper presents an adaptive encoding framework for the reduction of transition activity in high-capacitance off-chip data buses, since power dissipation associated with those buses can be significant for high-speed communication. The technique relies on the observation of data characteristics over fixed window sizes and formation of cluster with bit lines having highly correlated switching patterns. The proposed method utilizes redundancy in space and time to prevent loss of information while retrieving data. We present analytical and experimental analyses, which demonstrate the activity reduction of our encoding scheme for various data. The extra power cost due to the encoder and decoder circuitry along with redundancy is offset due to reduced number of off-chip transitions.