Platforms with multiple cores are now prevalent everywhere from desktops and graphics processors to laptops and embedded systems. By adding more parallel computational resources while managing power consumption, multicore platforms offer better programmability, performance, and power efficiency. Signal processing systems of tomorrow will be and must be implemented on platforms with multiple cores. Writing efficient parallel applications that utilize the computing capability of many processing cores require some effort. Signal processing algorithm designers must understand the nuances of a multicore computing engine; only then can the tremendous computing power that such platforms provide be harnessed efficiently. To give a thorough perspective of the area, we have organized two special issues on this topic.

Platforms with multiple cores are now prevalent everywhere from desktops and graphics processors to laptops and embedded systems. By adding more parallel computational resources while managing power consumption, multicore platforms offer better programmability, performance, and power efficiency. Signal processing systems of tomorrow will be and must be implemented on platforms with multiple cores. Writing efficient parallel applications that utilize the computing capability of many processing cores require some effort. Signal processing algorithm designers must understand the nuances of a multicore computing engine; only then can the tremendous computing power that such platforms provide be harnessed efficiently. To give a thorough perspective of the area, we have organized two special issues on this topic.

P latforms with multiple cores are now prevalent everywhere from desktops and graphics processors to laptops and embedded systems. By adding more parallel computational resources while managing power consumption, multicore platforms offer better programmability, performance, and power efficiency. Signal processing systems of tomorrow will be and must be implemented on platforms with multiple cores. Writing efficient parallel applications that utilize the computing capability of many processing cores require some effort. Signal processing algorithm designers must understand the nuances of a multicore computing engine; only then can the tremendous computing power that such platforms provide be harnessed efficiently. To give a thorough perspective of the area, we have organized two special issues on this topic. The first special issue, published in November 2009, provided an overview of multiple core systems along with some key methodologies. The articles provided coverage of key trends and emerging directions in architectures, design methods, software tools, and application development for the design and implementation of multicore signal-processing systems. There were three articles surveying the multicore architectures, from generalpurpose processors and digital signal processors (DSPs) to multiprocessor system-on-chip. These were followed by four articles discussing software development methodology, including compilation tools that discover parallelism automatically, parallel programming languages where programmers can annotate the parallelism, and approaches that require programmer to explicitly express the parallelism. Part 1 of the two-part special issue ended with four design-example articles spanning fast Fourier transform (FFT), video processing, video coding, and speech recognition. This special issue aims at 1) describing novel applications that can be enabled by platforms with multiple cores and 2) providing more extensive design examples to demonstrate useful techniques for developing efficient signal processing applications on platforms with multiple cores. Because multicore processors provide better programmability, performance, and power efficiency, many computationally

Multicore processors are now prevalent in all major domains of signal processing. Many laptop and desktop computers today are shipped with dualcore and even quad-core processors. The number of cores is even higher for the Sony PlayStation 3, which is equipped with an 8-core IBM CELL Broadband Engine processor, Nvidia GeForce 9800 GX2, which has 256 stream processors, and SUN UltraSPARC T1/T2 proce...

The fast pacing diversity and evolution of wireless communications require a wide variety of base-band implementations within a short time-to-market. Besides, the exponentially increased design complexity and design cost of deep sub-micron silicon highly desire the designs to be reused as much as possible. This yields an increasing demand for reconfigurable/programmable baseband solutions. Implementing all baseband functionalities on programmable architectures, as foreseen in the tier-2 SDR, will become necessary in the future. However, the energy efficiency of SDR baseband platforms is a major concern. This brings a challenging gap that is continuously broadened by the exploding baseband complexity. We advocate a system level approach to bridge the gap. Specifically, we fully leverage the advantages (programmability) of SDR platforms to compensate its disadvantages (energy efficiency). Highly flexible and dynamic baseband signal processing algorithms are designed and implemented to exploit the abundant dynamics in the environment and the user requirement. Instead of always performing the best effort, the baseband can dynamically and autonomously adjust its work load to optimize the average energy consumption. In this paper, we will introduce such baseband signal processing techniques optimized for SDR implementations. The methodology and design steps will be presented together with 3 representative case studies in HSDPA, WiMAX and 3GPP LTE.

The wide range of future and existing standards in wireless communications calls for flexible solutions. A way to intro- duce flexibility to digital radio systems is to replace hardwired components by programmable devices. This paper describes the exploration of a VLIW architecture targeting the domain of multimode wireless baseband process- ing. Target is to explore the tradeoff between flexibility, per- formance and power consumption. The Coware® LISATek™ tool suite for automated embedded processor design has been used to create a processor model with scalable number of functional units and RTL generation capability. Furthermore, a C-compilation framework based on IMPACT was adapted to enable the mapping of a Fast Fourier Transformation and parts of a SDM-OFDM receiver. The code was optimized with special instruction supported in C by in- trinsic functions. To estimate the costs of the implemented optimization, the generated RTL has been synthesized in 90nm technology. It is shown that a wide energy-performance tradeoff can be ranged by varying the processor configurations. Moreover, by using special instructions for complex arithmetic, power con- sumption and execution time of the benchmarked kernels can be reduced by factor two.

Software Defined Radio (SDR) terminals are crucial to enable seamless and transparent inter-working between fourth generation wireless access systems or communication modes. On the longer term, SDRs will be extended to become Cognitive Radios enabling efficient spectrum usage. Future communication modes will have heavy hardware resource requirements and switching between them will introduce dynamism in respect with timing and size of resource requests. In this paper, we propose a modeling framework that enables the simulation of such complex, dynamic hardware/software SDR designs. Thus, we can do an exploration, which can pinpoint the coarse grain platform component requirements for future SDR applications in a very early design phase. Our solution differs from existing ones by combining multiple simulation granularities in a way that is specialized for SDR simulation. Finally, we demonstrate the effectiveness of our approach with a case study for dimensioning the on-chip interconnect of a prospective SDR platform.

Multicore processors are now prevalent in all major domains of signal processing. Many laptop and desktop computers today are shipped with dualcore and even quad-core processors. The number of cores is even higher for the Sony PlayStation 3, which is equipped with an 8-core IBM CELL Broadband Engine processor, Nvidia GeForce 9800 GX2, which has 256 stream processors, and SUN UltraSPARC T1/T2 processor, which has 8 cores. Technology predictions indicate that this trend will continue and that the number of cores per processor can easily double around every two or three years.

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.

Emerging SDR baseband platforms are usually based on multiple DLP+ILP processors with massive parallelism [10]. Although these platforms would theoretically enable advanced SDR signal processing, existing work implemented basic systems and simple algorithms. Importantly, MIMO is not fully supported in most implementations [7][9][11]. [1] implemented MIMO but with a simple linear detector. Our work explores the feasibility for SDR implementations of soft-output ML MIMO detectors, which brings 6--12 dB SNR gains when compared to popular linear detectors. Although soft-output ML MIMO detectors are considered to be challenging even for ASICs [3][4], we combine architecture-friendly algorithms, application specific instructions, code transformations and ILP/DLP explorations to make SDR implementations feasible. In our work, a 2x4 ADRES based ASIP with 16-way SIMD can deliver 193Mbps for 2x2 64QAM, and 368Mbps for 2x2 16QAM transmissions. To the best of our knowledge, this is the first work exploring SDR based soft-output ML MIMO detectors.

This paper describes the implementation of an energy-efficient digital SDR baseband platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS technology and occupies 32mm2. It incorporates all digital signal processing required by the physical layer of the WiFi(802.11n), WiMax(802.16e), mobile TV and 3GPP-LTE standards. The heterogeneous architecture with hierarchical wake-up achieves 5mW idle time power, is capable of delivering a net data rate in excess of 200Mbps and consumes 231mW during 108Mbps WLAN 2×2 MIMO Rx, achieving 2.14nJ/b energy efficiency.

Advances in low-power and low-cost sensor networks have led to solutions mature enough for use in a broad range of applications varying from health monitoring to building surveillance. The development of those applications has been stimulated by the finalization of the IEEE 802.15.4 standard, which defines the medium access control (MAC) and physical layer for sensor networks. One of the MAC schemes proposed is slotted carrier sense multiple access with collision avoidance (CSMA/CA), and this paper analyzes whether this scheme meets the design constraints of those low-power and low-cost sensor networks. The paper provides a detailed analytical evaluation of its performance in a star topology network, for uplink and acknowledged uplink traffic. Both saturated and unsaturated periodic traffic scenarios are considered. The form of the analysis is similar to that of Bianchi for IEEE 802.11 DCF only in the use of a per user Markov model to capture the state of each user at each moment in time. The key assumptions to enable this important simplification and the coupling of the per user Markov models are however different, as a result of the very different designs of the 802.15.4 and 802.11 carrier sensing mechanisms. The performance predicted by the analytical model is very close to that obtained by simulation. Throughput and energy consumption analysis is then performed by using the model for a range of scenarios. Some design guidelines are derived to set the 802.15.4 parameters as function of the network requirements.

User demand, standards and products for digital nomadic communications are evolving quickly. The combination of this changing environment together with the need for short time-to-market pushes for more flexible implementations. Software Defined Radios (SDR) have been introduced as the ultimate way to achieve such flexibility. The reduced energy budget required by battery-powered solutions makes the typical worst-case static dimensioning unaffordable under highly dynamic operating conditions. Instead, more energy-scalable algorithms and implementations are entailed to provide flexibility while maintaining the required energy efficiency. Particularly, energy-scalable implementations can exploit data format properties to offer different tradeoffs between accuracy and energy. In this paper, such a technique is developed and applied to the SDR implementation of a 2 antennas 200 Mbps+ OFDM (Orthogonal Frequency-Division Multiplexing) inner modem receiver on a C-programmable CGA (Coarse Grain Array) processor with extensive SIMD (Single Instruction Multiple Data) support. By defining separate implementations for different combinations of modulation scheme and coding rate, up to 3-fold gains can be achieved in the average energy consumption.

The continuously increasing number of communication standards to be supported in nomadic devices combined with the fast ramping design cost in deep submicron technologies claim for highly reusable and flexible programmable solutions. Software defined radio (SDR) aims at providing such solutions in radio baseband architectures. Great advances were recently booked in handset-targeted SDR, covering most of the baseband processing with satisfactory performance and energy efficiency. However, as it typically depicts a magnitude higher computation load, forward error correction (FEC) has been excluded from the scope of high throughput SDR solutions and let to dedicated hardware accelerators. The currently growing number of advanced FEC options claims however for flexibility there too. This paper presents the first application-specific instruction programmable architecture addressing in a unified way the emerging turbo- and LPDC coding requirements of 3GPP-LTE, IEEE802.11n, IEEE802.16(e) and DVB-S2/T2. The proposal shows a throughput from 0.07 to 1.25 Mbps/MHz with efficiencies round 0.32 nJ/bit/iter in turbo mode and round 0.085 nJ/bit/iter in LDPC mode. The area is lower than the cumulated area of dedicated turbo and LDPC solution.

Since Low-Density Parity-Check (LDPC) codes deliver excellent decoding performance, they are adopted in several recent communication standards like the IEEE 802.11n, IEEE 802.16e and DVB-S2. This raises the need for multi-standard, multi-mode decoder architectures. In this paper we propose to use the min-sum approximation together with a turbo-like decoding approach for decoding LDPC codes, and afterwards we perform a global trade-off analysis which enables the designer to choose the appropriate decoding algorithm.

Advances in low-power and low-cost sensor networks have led to solutions mature enough for use in a broad range of applications, requiring various degrees of reliability. To facilitate this, a broad range of options are possible to tune reliability, throughput or energy cost in the IEEE 802.15.4 standard defining the medium access control (MAC) and physical layer for sensor networks. Knowing how to tune those knobs however requires detailed models of the protocol behavior under different conditions. In our earlier work, we have proposed a very accurate model for the slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) access scheme of the IEEE 802.15.4 standard for the unacknowledged transmission mode. Because of the design of the 802.15.4 carrier sensing mechanism, modeling the performance of the network in case of acknowledged transmissions is not a trivial extension. In this paper, we hence derive such model and illustrate through simulations that it is extremely accurate. Next, using the model, guidelines are derived to optimize the energy or throughput performance of sensor networks using the IEEE 802.15.4 standard.