Today through-silicon via (TSV) is a mature process technology option for manufacturing of 3D stacked integrated circuits (3D-SIC). This chapter shows the results of the system-level/process technology co-design analysis. It presents a design flow for carrying out exploration of 2D and 3D-SIC implementations. The chapter considers multiple variations of a complex mobile MPSoC platform instantiated for real-life streaming wireless applications. It focuses on Cu-Cu bonding-based face-to-face (F2F) stacking in the case of 3D-SIC implementations because it carries out fine-grained memory-on-logic 3D partitioning, resulting in 2-layer 3D-SIC implementations with very large number of inter-die connections. It uses the following three factors to broadly classify different technology options: (i) integration granularity, (ii) stacking orientation, and (iii) TSV formation. The chapter presents a a case study where it explores 2D and 3D-SIC implementations for mobile MPSoC platform targeted at wireless baseband processing. It also considers ultrafine pitch 3D interconnections using Cu-Cu pad bonding and F2F stacking.

This paper presents an accurate technique to extensively analyze the impact of time-zero (i.e., global and local variation) and time-dependent (i.e., voltage, temperature, workload, and aging) variation on the offset voltage specification of a memory sense amplifier design using 45 nm predictive technology model (PTM) high performance library. The results show that increasing the supply voltage both for time-zero and time-dependent reduces the offset voltage specification marginally, irrespective of the process corners. In contrast, the offset voltage specification is very sensitive to the temperature and the workload, i.e., the applied voltage patterns. The results also show that a balanced workload results in a significantly lower offset voltage specification. The above results can be used to estimate the required offset voltage accurately for a given lifetime, and operational conditions such as workload, temperature, and voltage; hence, enable the designer to take appropriate measures for a high quality, robust, optimal and reliable design.

In imec predictive N5 technology platform (poly pitch 42nm, metal pitch 32nm), enabling cell height reduction from 6 to 5 tracks constitutes an interesting opportunity to reduce area of digital IP-blocks without increasing wafer cost. From a physical point of view, the two main challenges of reducing the number of tracks are posed by the increased difficulty of completing inter-cell connections in standard cell design, and by increased pin density that makes more challenging for the router to maintain high placement densities. Both these issues can potentially result into cell and chip area enlargement, thus mitigating or canceling the benefits of moving to 5-Tracks. In this study this side effect was avoided through a careful Design-Technology Co-Optimization approach (DTCO) [1], where a set of design arcs was used in conjunction with an EUV compatible ruleset that allowed efficient 5-Tracks standard cell design, resulting in final area gains up to 17% that were validated through a commercial state-of-the-art Place and Route (P&R) flow.

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore's law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide <50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm2 of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length.

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-the-art P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative. (C) 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)

In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.

In this paper, we study the impact of different device architectures and material properties on the performance of two-dimensional tunnel FETs (2D TFETs). We show that single-gate (SG) device architecture in case of monolayer and few layers two-dimensional materials perform better than doublegate (DG) architecture. Due to sharper band bending at the tunneling junction, SG device offers shorter tunneling lengths resulting in larger ON currents. With physical insight into the device structure, we show that the gate-to-source outer fringing fields play a significant role in 2D TFETs performance. In order to reduce the effect of outer fringing fields, we propose a device structure with an interfacial layer (IL) between High-k and 2D material, resulting a 3-4× increase in ON current. Further, we show that ON currents can be further boosted by increasing the channel thickness. In the end, it is shown that a bi/tri-layer anisotropic 2D material based SG/DG TFET using IL can provide up to 400% higher ON current in comparison to monolayer 2D material based SG FET for equivalent effective mass and bandgap.

In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal pitch 21 nm and achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by power and performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 nm width are competitive with FinFETs made with two fins while relaxing the constraints on layout design rules.

In this letter, we have studied the impact on lateral nanowire transistor's (LNW) performance of reducing the wire diameter from 7 nm to 5 nm. As technology scaling continues, the LNW device size is scaled here for beyond 7-nm nodes. Reducing the NW's gate length causes huge degradation in electrostatic control of the device. The degraded electrostatic is improved by reducing the wire diameter. DC and ring oscillator benchmark have been performed for different NW size for sub-7-nm node using TCAD-based compact models. Using the 5-nmdiameter- based LNW at the gate length of 10 nm around 8-mV/decade subthreshold slope improvement is observed as compared with the 7-nm-diameter LNW. This leads to the possibility of improved performances for the 5-nm-diameter-based device. The NW device, with 5-nm wire diameter and 10-nm gate length can provide some area gain. Although the 5-nm-diameter device increases channel confinement, due to the reduced drive current and increased parasitics, over-all device speed is lagging behind the 7-nm diameter device.

SummaryA novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at VDD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.

The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.

At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff performance, power, area and manufacturability. However, implementation platforms don't typically have access to process information and process teams don't have complete design knowledge. Also, optimization loops required for Design-Technology-Co-Optimization (DTCO) are either impossible or at best long and expensive for fabless design house. Joining forces, ASML, IMEC and Cadence Design Systems developed an In-design and signoff lithography physical analysis well suited for 7/5nm and below. The Tachyon OPC+ and LMC engines used by IMEC 7/5nm process has been integrated in Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process models, recipes, and hotspot detectors. This flow leverages existing LPA infrastructure for both custom and digital design platforms, as well as standalone signoff. Depending upon the end application, LPA could be launched either from place & route, custom layout or standalone. LPA PLUS processes first the design database to identify hierarchy, decompose the layout for coloring and apply pattern matching to identify location requiring simulation. The layout is then passed to the Tachyon OPC+ engine to perform optical proximity correction and to Tachyon LMC engine for model-based litho verification that is validated on Silicon. The hotspots and contours are processed by LPA PLUS for generation of hotspot marker and fixing guidelines. It then provides all this information to the design environment. The flow has been developed and demonstrated to work on IMEC 7nm, and can be ported to smaller or larger technologies. This paper will present the result of this In-design and signoff lithography physical analysis flow, how DTCO and design teams can add manufacturability to PPA.

Making standards cells smaller by lowering the cell height from 7.5 tracks to 6 tracks for the same set of ground rules is an efficient way to reduce area for high density digital IP blocks without increasing wafer cost. Denser cells however also imply a higher pin density and possible more routing congestion because of that. In Place and Route phase, this limits the cell density (a.k.a. utilization) that can be reached without design rule violations. This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Standard cells have been created for 7.5T and 6T cells in N5 technology (poly pitch 42nm, metal pitch 32nm). The cells use a first horizontal routing layer (Mint) and vertical M1 for 1D intra-cell routing as much as possible. Place and route was performed on an opencores LDPC decoder. Various cell architectures and place and route optimizations are used to scale down the cell area and improve density. Most are not process optimizations, but optimized cell architectures and routing methods: • Open M1: M1 is removed as much as possible. This allows the router to use M1 for inter-cell routing in dense areas. • Routing in Mint: With open M1 the router can also use Mint to extend pins to access nearby free M1 tracks in congested areas. • Outbound rail: The 7.5T cells have inbound VDD/VSS rails in Mint for easy supply tapping. Moving the Mint rail outbound and shared between cells is required to enable lower track height cells. • Vertical Power distribution network (PDN): in 6T cells too many horizontal tracks would be consumed by the wide M2 rail. Mint is used instead combined with a vertical PDN in M1. • Self-Aligned Gate Contact allows to contact the gate on top of active fins. Any Mint track then can contact a gate, reducing cell area considerably. • Partially landing Mint Via trench: In 6T cells, a continuous Via trench underneath the Mint rail is used. This via partially lands on M0A to relax tip-to-tip requirements. • Relaxed M2 pitch: When pin access is handled in Mint and M1, this allows for a relaxed M2 pitch (48nm) with cheaper double patterning. To avoid horizontal routing layer congestion with the smaller cells, the 6T cells depend on the vertical PDN and open M1 to improve routability and pin access. Already in 7.5T cells, open M1 and vertical PDN help to improve routable utilization from 50% with closed M1 to 85% maximum. Moving to 6T cells, the combination of reduced cell area and high 85% utilization of result in a 60% area reduction vs the original 7.5T cells. We have shown that combining 6-track cells and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Open M1 and vertical PDN are main area boosters for any cell architecture, boosting utilization from 50% to 85% already for the 7.5T cells.

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Spin-transfer torque magnetoresistance random access memory is a major contender for static random access memory replacement in embedded caches at advanced fin field effect transistor nodes. It suffers, however, from the low resistance difference between the bistable states of the magnetic tunnel junction (MTJ). Variability on MTJ resistance and access transistors makes reliable read-out even more challenging. This triggered the use of complementary cells for low level caches needing high performance. This paper, focusing on the lower level caches, shows an improved 3T 2MTJ cell with a ground grid and a novel three transistor read and write operation to improve area density, sense margin, write performance, and write energy consumption. Despite the cell's three transistors, the improved array configuration reduces the cell area by 22% as compared with the 2T 2MTJ cell, making it only 55% larger than a 1T 1MTJ cell. The novel mismatch tolerant read operation uses all three transistors and increases the sense margin by up to 88%. The novel variation resilient write operation also uses all three transistors and takes advantage of the inherent MTJ characteristics and complementary operation of the cell. This increases the write performance by 2x and reduces the write energy by 3x compared with the 2T 2MTJ cell and by 1.5x compared with the 1T 1MTJ cell.

Self-aligned multiple patterning, due to its low overlay error, has emerged as the leading option for 1-D gridded back-end-of-line (BEOL) in sub-14-nm nodes. To form actual routing patterns from a uniform “sea of wires,” cut masks are needed for line-end cutting or realization of space between routing segments. The line-end cutting results in nonfunctional (i.e., dummy fill) patterns that change wire capacitance, and hence design timing and power. Therefore, to remove such dummy fill patterns, extra 2-D block masks are used. However, 2-D block masks cannot remove arbitrary dummy fill patterns, due to design rule constraints on the block mask shapes. In this paper, we address the timing-aware optimization of 2-D block mask layouts under various sets of mask rules that are derived from mask patterning technology options (e.g., 193i and 193d) for foundry 7-/5-nm (N7/N5) BEOL. Our central contribution is a mixed integer linear programming (MILP) optimization that minimizes timing impact due to dummy metal segments while satisfying block mask rules and metal density constraints. We also propose a distributed optimization flow to improve the scalability. With our optimizer, we recover up to 84% of the worst negative slack impact from dummy segments, with up to 64% dummy removal rate. We further extend our MILP to a co-optimization of cut and block masks. This paper gives new insights into fundamental limits of benefit from emerging cut and block mask technology options.