Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSV's, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

High performance radio frequency (RF) technology is required for many communications applications, such as mobile phones. The interconnects for RF circuits are different from those for digital circuits in a number of ways, including thick wiring layers (>; 3 μm), extensive use of passive devices such as thin film resistors, metal-insulator-metal (MIM) capacitors, and inductors, and use of through-silicon vias (TSVs) for ground planes. As a result, there are a number of unique reliability challenges for these devices, including controlling stress in thick wiring layers and TSVs, and ensuring reliability of MIM capacitor dielectrics. In this paper, we will describe process optimization and reliability evaluation for interconnects in RF circuits.

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume lead-free interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mOmega. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications.

Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm2, 400 I/O/mm2, and interconnection features sizes which support 2500 I/O / mm2. In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm2 per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die o- n a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed.

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based oil a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 m Omega and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the "vias-first" and the "vias-last" methods, along with related advantages and potential drawbacks of each. Improvement to these process flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results oil via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.

As chip I/O count continues to increase, the C4 bump pitch needs to be further reduced. In this work, a Si-based test carrier was used for characterization of ultra-fine pitch micro C4s. Successful assembly and rework of die with 11,892 micro C4s were demonstrated. The micro C4 contact resistance was measured for various pad geometries. The mechanical shear force was characterized for several variables including contact pad area, pad shape, and shear direction. When joined onto pads with reduced size, the micro C4s were sheared without significant damage. Therefore, a carrier with reduced-size bonding pads can be utilized as a platform for functional test and burn-in followed by chip removal to create know-good-die (KGD). These high I/O KGD can be joined to a multi-chip module, silicon package or stacked to create chip stacks and tested to create known-good-modules (KGM) or known-good-die-stacks (KGDS). This specialized high I/O silicon carrier with full area array, reduced-area bonding pads is also referred to as a temporary chip attachment (TCA) substrate.

In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 times 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of ~10 mOmega are typical, and through-via yields of 99.98% at module level have been demonstrated

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

A high-speed process for servowriting hard-disk assemblies (HDAs) without an external clock head has been developed. This robust process achieves servo-pattern alignment accuracy comparable to or better than that achieved with conventional clock-head based servowriters at a substantially reduced capital and process cost

We report the derivation and experimental verification of a simple model of the high frequency permeability of narrow soft-magnetic thin film structures which includes eddy currents and magnetization rotation, wall motion, and saturation. Data is presented for long narrow magnetic rectangles with the idea that common thin-film magnetic structures, such as recording heads, can be are modelled as connected stripes of different widths. The easy magnetic axis is aligned perpendicular to the applied field and to the long axis of the stripes. The model bas two terms: from the easy-axis aligned domains, the bulk permeability (magnetization rotation) reduced by eddy currents and the constriction due to closure domains, and from the hard axis regions, domain wall motion described by the standard damping limited theory of wall motion solved for an oscillatory field. Saturation is handled by clipping the total moment change at 4-pi-M(s) and replacing the wall phase delay with the transit time for a wall to cross the film.

The magnetic and structural properties of ferromagnetic FeN thin films. FeN/FeN (ferromagnetic/paramagnetic) and FeN/SiO2 multilayers deposited in a rotational dc magnetron sputter system were investigated. Monolithic films containing ⋍ 2at% N2had 4πMs, values ⋍ 25 kG magnetostriction (λs) has been related to N2 content and film thickness. λs could be varied significantly over a range of compositions where 4πMs was > 22 kG by adjusting thickness and nitrogen. content. Lamination reduced easy- and hard-axis coercivity to < Oe. Lorentz microscopy indicated that the ferromagnetic FeN layers in the FeN/FeN films were exchanged coupled while those in the FeN/SiO2 films were magnetostatically coupled.

We have constructed a high-frequency permeameter to measure the magnetic response of magnetic thin-film stripes to sinusoidally oscillating rf magnetic fields of up to 5 Oe over the frequency range from 300 kHz to 30 MHz. These fields simulate those used to drive magnetic heads allowing the magnetic dynamics during recording of the magnetic thin-films in a recording head to be studied in a much simpler geometry. Measurements were performed on single and multi-layer permalloy thin-films, photolithographically patterned into arrays of 3-mu-m to 1000-mu-m wide rectangles, 1 cm long. The low field-amplitude permeability of narrow unlaminated permalloy stripes is frequency independent except for eddy current losses as expected for magnetization rotation. At higher fields the magnetic response increases at frequencies below 10 MHz with increasing drive amplitude as domain wall motion becomes significant (as is seen in heads). Our results are consistent with the expected domain wall mobility (around 2 x 10(3) cm/(s-Oc) for 2-mu-m thick films). At still higher fields the permeability drops as the film saturates above H(c). Because of the high density of walls in microscopic structures, wall motion is the dominant flux conduction mechanism below 30 MHz at high drive fields. This means that wall oscillations (seen in dynamic-Kerr images of recording heads) determine the head response below 30 MHz during writing.

The permeability of the magnetic material in a thin-film magnetic head is an important, but hard to characterize, parameter since the magnetic permeability depends on the head domain structure, the drive frequency, and the shape and size of the head. We have measured the high-frequency permeability from 1 MHz to 300 MHz, hysteresis loops, and domain structure of unlaminated and multilayer magnetic thin-films as a function of stripe width for arrays of long narrow stripes. Monolithic permalloy films and permalloy films laminated with SiO2 have been photolithographically patterned and ion-milled to create 3 to 1000 μm wide rectangles, 1 cm long, with the hard axis oriented along the long axis of the rectangles. The high-frequency permeability of each array of a given width is measured by the signal detected by a nonresonant butterfly-coil pickup loop when the film is driven by a uniform radio-frequency magnetic field generated by a strip-line waveguide. The changes in domain pattern as the film structure and stripe width are varied are observed with a Kerr-effect imaging microscope. In unlaminated films, which exhibit standard closure domains, a reduction in high-frequency permeability is observed in agreement with simple models when the closure domains become a significant fraction of the film area. In laminated films with thick magnetic layers, the transition from the laminated domain state to closure domains as the stripe width is decreased occurs where expected from straightforward energy arguments. However, for magnetic layers less than 1 μm thick, where a transition from the easy-axis laminated domain state to a uniform hard-axis state is expected as the stripe width is reduced, the films first change from the easy-axis state to a complicated, low-Kerr-contrast domain pattern before switching to the hard-axis state at much larger widths than predicted. While the laminated state and hard-axis permeabilities are frequency independent, the permeability of the intermediate state rolls off beginning at between 10 and 100 MHz. For still thinner magnetic layers (250 Å), the multilayer retains the high-permeability easy-axis laminated domain state to the narrowest width measured, 3 μm.

Multilayered Ni/sub 80/Fe/sub 20//SiO/sub 2/ films have been produced by sputter deposition. The effects of lamination on the bulk magnetic properties, microstructure, and high-frequency permeability of stacks with various Ni/sub 80/Fe/sub 20/ and SiO/sub 2/ thicknesses were investigated. In general, laminated films with a total magnetic thickness of 1.5 mu m had significantly lower H/sub c/ and extended frequency response, compared to unlaminated films of the same magnetic thickness. In addition, the impact of lamination on domain configuration of yoke-shaped structures was determined, and excellent agreement with micromagnetic theoretical prediction was obtained. >

The thermomagnetic writing and erasure of submicron domains has been observed in a magneto-optic thin film using the anomalous Hall effect (AHE) voltage generated within the medium itself. A TbFeCo film has been photolithographically patterned to form a cross-shaped Hall geometry a few microns across. The AHE voltage, proportional to a weighted average of the transition metal magnetization within the cross, is affected by a laser pulse in two ways. First, the laser heats the film, reducing the magnitude of the magnetization. Secondly, the sign of the AHE voltage changes as the magnetization reverses within the written domain. A time resolution if 100 ns, has been obtained, and better than 10 ns resolution should be achievable. The technique has been used to make quantitative laser-induced writing as a function of laser pulse energy and external field

In high-frequency magnetic structures (like thin-film magnetic heads) which have been laminated to avoid eddy current loss, it is standard to assume that electromagnetic coupling across the dielectric separating the magnetic layers is small. We show that for macroscopic films with insulating interlayers, the laminated structure is better modeled by an anisotropic effective medium with a magnetic permeability of around 3000 but an insulating dielectric function perpendicular to the lamination plane, while still metallic parallel to the lamination plane. Electromagnetic waves can propagate parallel to the lamination direction but with 1/100 of the free-space wavelength. The electromagnetic (capacitive) coupling between the layers can lead to radically altered propagation of magnetic flux and generate novel permeance resonances caused by interference effects across the width of the film. A Fourier series solution constructed with a mean-field theory for the wave equation for laminated slab geometries predicts the permeance resonances observed experimentally.

The previously unmapped Bolivian sector of the Central Brazil Shield, ∼220 000 km in area, has been studied during an Anglo-Bolivian technical co-operation programme. The metamorphic basement comprises the Lomas Maneches Granulitic Complex, the Chiquitania Gneissic Complex and the San Ignacio Schist Supergroup which crops out as metasedimentary belts. Rb-Sr dates on some of the granulites suggest a protolith age of ∼ 2000 Ma, but the outcrop pattern of the metamorphic rocks as a whole is due to the ∼ 1300 Ma San Ignacio Orogeny, which was accompanied by widespread granite emplacement and metamorphism up to granulite facies. The Sunsas Cycle began with the deposition of the supracrustal Sunsas/Vibosi Group and closed with the development of the Sunsas and Aguapei Mobile Belts at ∼ 1000 Ma. The Upper Proterozoic Brasiliano Cycle is represented by a bifurcating sedimentary basin in the SE of the area with a closing tectonic event of ∼ 520 Ma.