Fine-pitch inter-strata connections in 3-D stacking lack rework solutions which can aide in early learning for 3-D integration. Reduced solder volume in the microbump or micropillar is also less tolerant to non-planarity and non-uniformity of the strata and interconnection array, especially as die size and number of interconnections increase. At fine pitch, heavily-loaded thermal underfills can have high viscosity and potential risk of filler entrapment. To address these issues, reworkable interconnections have been fabricated in our facility. In these structures, sharp metal tips were formed in a silicon mold and transferred to a silicon substrate to form one side of the reworkable interconnect. The other side of the reworkable interconnect is a silicon substrate with lead-free microbumps coated with underfill. The two silicon substrates were brought into contact at room temperature without reflowing the solder to perform electrical test. . The temporary stack can be easily separated (reworked) if test results indicate failure. Non-planarity is tolerated up to an amount which is the lesser of the height of the tips and solder thickness. A test vehicle with approximately 45,400 pairs of reworkable interconnects at 50 μm pitch was fabricated. Contact resistance as low as 115 mΩ was obtained at a contact force of 0.2 g per interconnect after insertion and partial cure. This same structure was also used to make initial permanent interconnects, the contact resistance measured 34 mΩ after reflow. Typical yield over the initial 10 mm × 12 mm test vehicles built was found to be > 99.9% out of 22,000 interconnects that can be electrically measured.

Two vertical probe technologies were explored to evaluate wafer-level and 3D stack-level die test at 50 μm pitch. In one approach, Cu probe tips were serially built on a 3D silicon wafer using lithography and wet chemical etching. In a second approach, metal probe tips were fabricated by filling a silicon mold made with anisotropic etching and transferred to a silicon die. Each approach had advantages which were demonstrated through test vehicles. The second approach appears promising to offer a robust, scalable probe technology, highly suited for high speed test of 3D die. As compared to traditional probe technologies, this approach also offers an opportunity toward low cost test at fine pitch.

Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSV's, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

The results of stress tests on 50 μm-pitch Pb-free microbump interconnect 3D Si structures are summarized. It was found that thermal processes alone compete strongly with electromigration at stress currents of 50 and 100 mA. Typical test sites exhibited a gradual increase in relative resistance increase over time. While large changes in bump interconnection resistance did occur for some sites, the interconnections were resistant to full open electrical failure, even after subjected to mechanical shock following long-term EM stress. Underfilled samples were more robust than non-underfilled samples. Overall, the results suggest that for application in 3D Si stacks, microbumps can support higher power densities than those used currently with standard pitch bump interconnections.

The kinetics of charge capture by deep donors in AlxGa1−xAs have been measured. The time dependence indicates that a single energy cannot be used to describe the trap. A model assuming thermally activated capture into a resonance in the conduction band with a range of energies gives excellent fits to the data and provides a measure of the energy range for the trap. This model is consistent with the large lattice relaxation model for DX centers. The increase of the activation energy for capture as the Al mole fraction is decreased contradicts the model which attributes the decay of the persistent photoconductivity to tunneling through the heterojunction barrier in modulation doped structures.

3D integration, using fine-pitch and high density vertical interconnects (TSVs), has been drawing considerable interest due to its promise for higher performance and smaller form factor. As the number of I/O increases and the pitch size decreases, interconnect joining process and reliability become critical in the assembly of 3D chip stacks. In this study, 3D chip stacks with more than 48,000 Pb-free solder micro-bump interconnects at 50 μm pitch were assembled and the joint reliability evaluated. Multiple bonding processes were developed, enhanced and characterized by investigating the influence of various bonding parameters such as atmosphere, compression mode and temperature profile on the joint formation. Various test vehicle sizes with multiple layers of thinned die were successfully assembled using the enhanced bonding profile. Underfilling of the narrow gaps between the stack dies was demonstrated using underfills with fine-particle fillers. The assembly yield and interconnection parasitic resistance was quantitatively studied as a function of the number of die layers. The reliability silicon die stacks integrated into modules with organic laminates was characterized by thermal cycling tests.

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm 2 to 10 8 /cm 2 ), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

We have developed a die-to-wafer integration technology for high yield and throughput for the formation of high bandwidth, high performance, and short-distance interconnections in three-dimensional (3D) stack applications. The results show that multiple 70-mum thick die can be successfully assembled in stacks on top of a wafer using a single bonding step, rather than by repeated sequential bonding steps. In this study, 1-die, 3-die, and 6-die stacks were assembled and the electrical resistance of link chains consisting of through-silicon-vias (TSVs), low-volume lead-free interconnects, and Cu wiring links was measured. The average resistance of the TSV including the lead-free interconnect was as low as 21 mOmega. The stacking throughput can be dramatically improved by this die-to-wafer integration technology and the contact resistance and reliability test results suggest that a reliable integration technology can be used for 3D stack applications.

Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm2, 400 I/O/mm2, and interconnection features sizes which support 2500 I/O / mm2. In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm2 per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die o- n a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed.

Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based oil a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 m Omega and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the "vias-first" and the "vias-last" methods, along with related advantages and potential drawbacks of each. Improvement to these process flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results oil via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.

In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed. Unlike standard 100-micron C4 solder balls, very small solder volumes (< 6 microns high) were investigated. The mechanical properties were evaluated by shear and impact shock testing, while scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the IMC layers in solder joins before and after annealing. It was found that Cu/Ni/In and Cu/In interconnections have slightly lower shear strength per bump. While these values were lower than the Cu/Sn joins, the Cu/Ni/In chips passed the impact shock test for a simulated heat sink mass of 27 g/cm2. The reasons for the differences in reliability of these metallurgies are discussed. 3D chip stacking using two-layers of chips with fine-pitch lead-free interconnects was demonstrated. The resistance of link chains comprising through-vias, lead-free interconnects and Cu links were measured using a 4-point probing method. The average resistance of the through-via including the lead-free interconnect was 21 mOmega.

As chip I/O count continues to increase, the C4 bump pitch needs to be further reduced. In this work, a Si-based test carrier was used for characterization of ultra-fine pitch micro C4s. Successful assembly and rework of die with 11,892 micro C4s were demonstrated. The micro C4 contact resistance was measured for various pad geometries. The mechanical shear force was characterized for several variables including contact pad area, pad shape, and shear direction. When joined onto pads with reduced size, the micro C4s were sheared without significant damage. Therefore, a carrier with reduced-size bonding pads can be utilized as a platform for functional test and burn-in followed by chip removal to create know-good-die (KGD). These high I/O KGD can be joined to a multi-chip module, silicon package or stacked to create chip stacks and tested to create known-good-modules (KGM) or known-good-die-stacks (KGDS). This specialized high I/O silicon carrier with full area array, reduced-area bonding pads is also referred to as a temporary chip attachment (TCA) substrate.

In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 times 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of ~10 mOmega are typical, and through-via yields of 99.98% at module level have been demonstrated

To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm 2 . The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process

A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm2. This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, character- - ization, and potential new applications

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, high-current, high-density bump interconnections can be achieved for Si-carrier technology

System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electro-optic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications and may serve high-performance computing applications. This paper discusses a few emerging technologies which offer opportunities for circuit integration on-chip as well as on-package using fine pitch interconnection, silicon wafer processing and silicon carrier packaging technology. Advanced silicon carrier package technology with fine pitch (50/spl mu/m) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16/spl times/ increase over standard chip I/O, a 20/spl times/ to 100/spl times/ increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers and mini-multi-chip modules (MMCM) which integrate heterogeneous dies forming a single "virtual chip".