The effectiveness of multiple electron cyclotron resonance (ECR) harmonics has been thoroughly investigated in context of high current drive efficiency, generally observed in fully non-inductive operation of the low aspect ratio EXL-50 spherical tokamak (ST) powered by electron cyclotron (EC) waves. The Fokker-Plank equation is numerically solved to obtain electron distribution function, under steady state of the relativistic nonlinear Coulomb collision and quasi-linear diffusion operators, for calculating plasma current driven by the injected EC wave. For the extra-ordinary EC wave, simulation results unfold a mechanism by which electrons moving around the cold second harmonic ECR layer strongly resonate with higher harmonics via the relativistic Doppler shifted resonance condition. This feature is in fact evident above a certain value of input EC wave power in simulation, indicating it to be a non-linear phenomenon. Similar to the experimental observation, high efficiency in current drive (over 1 A/W) has indeed been found in simulation for a typical low density ($\sim 1\times10^{18}~m^{-3}$), low temperature ($\lesssim 100$ eV) plasma of EXL-50 by taking into account multi-pass absorptions in our simulation model. However, such characteristic is not found in the ordinary EC-wave study for both single-pass and multi-pass simulations, suggesting it as inefficient in driving current on our ST device.

In this paper, we propose a subsystem architecture under 3D-Storage Class Memory (3D-SCM), termed SuS, to solve the memory and power wall problems. Placing the processing unit under the 3D-SCM achieves high performance. We evaluate SuS using gem5 and the GPGPU-Sim simulator. The simulation results for the central processing unit (CPU)-based SuS architecture reveal a 100% performance improvement and a 73% energy reduction compared to the CPU architecture using dual in-line memory modules and a 4% performance improvement with a 27% energy reduction compared to the CPU architecture using hybrid memory cube. Moreover, the graphics processing unit (GPU)-based SuS architecture simulation results on the neural network benchmark demonstrate performance improvements of 17% and 7% compared to GPU architectures with graphics double data rate series memory and high bandwidth memory, respectively.

There is a growing demand for embedded non-volatile memory (eNVM) in Internet of Things (IoTs). Phase change memory (PCM) is a promising candidate for next generation eNVM with excellent CMOS process compatibility. Deep trench isolation (DTI) process is one of the extra steps to generate the diode selectors for PCM cells under 40 nm CMOS process. In this paper, we propose a 40 nm Non-volatile Standard cell Library (NSL) by reusing the DTI process to minimize the space among active areas. Thus, benefit from the embedded PCM (emPCM) process, the area of logic circuits can be reduced by using NSL. To verify the validity of the NSL, four ring oscillators are fabricated by using the normal standard cell library and NSL. The measured results show that the circuits by NSL work well and there is almost no performance sacrifice.

This paper proposes a multi-core architecture with asynchronous clocks to prevent power analysis attacks for the first time. The multi cores normally execute different tasks with default clocks, but will execute the cryptographic algorithm together with asynchronous clocks to foil the side channel attacks. The cryptographic algorithm is split into multi parts, each of which is executed simultaneously by one core. Security analysis and simulation results show that the differential power analysis (DPA) attack and correlation power analysis (CPA) attack fail on data encryption standard (DES) and advanced encryption standard (AES) with the proposed architecture.

With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

Modern data appliances face severe bandwidth bottlenecks when transferring data between storage and host. In this paper, we present a storage system which can improve performance more than three times by using an FPGA to implement the off- load engine. Regardless of the data size, the host CPU utilization varies vastly between the two systems, traditional way uses 100% and the system presented only uses 1%. Compared to the traditional way, the memory allocation has been greatly reduced. The system presented is explored for emerging NVRAMs which have many benefits compared to the traditional memory.

The endurance characteristics of phase change memory are studied. With operational cycles, the resistances of reset and set states gradually change to the opposite direction. What is more, the operational conditions that are needed are also discussed. The failure and the changes are concerned with the compositional change of the phase change material. An abnormal phenomenon that the threshold voltage decreases slightly at first and then increases is observed, which is due to the coaction of interface contact and growing active volume size changing.

Hybrid memory comprised of a big SCM and a little DRAM (BSLD) is widely studied to address the growing power consumption challenge of pure DRAM. However, the performance degradation, limited endurance and immature mass production of ultra-high-density SCM are still the painful points of BSLD. Here we propose a Retention-Aware Hybrid Main Memory (RAHMM) architecture with a big DRAM and a little SCM (BDLS) for the first time. DRAM is refreshed at a much longer interval by using SCM to store the small quantity of leaky tail bits in DRAM. A two-step search technology combined with outcome forecasting is put forward to get ultra-fast read access, as well as to diminish the power and performance overheads. A hidden buffer strategy (HBS) is proposed to optimize write performance and endurance hurt. The experimental results show 45 percent reduction of power consumption and 30 percent performance optimization, which are significantly improved compared to that of both serial and parallel BSLD with a counterpart capacity

Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can’t be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

A 16-Mb mask read-only memory (ROM) chip based on a novel diode structure is proposed. The diodes are constructed by buried n-type implantation layer and heavily doped p-type diffusion layer. With dual-trench isolation process and borderless contact scheme, the diode array can realize ultrahigh density. The fabricated mask ROM chip using 40-nm CMOS bulk technology is wired with three levels of metal, only two levels for diode arrays. The effective diode size is as small as 0.017 mu m(2), which is the smallest bitcell of commercial mask ROM products in the world, to our best knowledge. The physical array density can achieve approximately 0.0225 mm(2)/Mb. Test results indicate that chip standby leakage current is <1 mu A at 25 degrees C and <3.5 mu A at 85 degrees C with 2.5 V supply voltage. Array standby leakage is <6.25 mu A/Mb at 25 degrees C and <18.75 mu A/Mb at 85 degrees C with 2.5 V supply voltage.

Ge44Sn14Te42 phase change material exhibits a higher crystallization temperature (∼221 °C), a larger crystallization activation energy (∼2.88 eV) and a better data retention ability (∼126 °C for 10 years) in comparison with those of Ge2Sb2Te5. A reversible switching between set and reset can be realized by an electric pulse as short as 10 ns for Ge44Sn14Te42 based phase change memory (PCM) cell. In addition, PCM based on Ge44Sn14Te42 shows endurance up to 2.7 × 103 cycles with a resistance of about two orders of magnitude on/off ratio.

The microstructure and thermal properties of Si-implanted Sb2Te3 were investigated. Crystalline Si-implanted Sb2Te3 film with relatively uniform composition depth profile was fabricated, which consists of Si4−x (0 < x < 1) ions and crystalline Sb2Te3. No separated Te phase was found. The crystallization activation energies of crystallization increase with Si dose from 5 × 1015 to 2.16 × 1016 Si-ions/cm2. The crystallization temperatures of the films are 149, 168, and 174 °C with 5 × 1015, 1 × 1016, and 2.16 × 1016 Si-ions/cm2 ion implantation, respectively. Furthermore, the Sb2Te3 film implanted with the dose of 1 × 1016 Si-ions/cm2 can maintain the data for 10 yr at 85 °C, which is comparable to Ge2Sb2Te5. The results indicate that the Si-implanted Sb2Te3 is a promising candidate for phase change memory application.

The Phase Change Memory (PCM) based on the rapid reversible phase change effect in the chalcogenide film has been regarded as one of the most promising candidates for the next-generation nonvolatile memories. The phase change material of Si2Sb2Te6 was newly proposed for phase change memory application, which has lower power consumption and better endurance than conventional Ge2Sb2Te5 materials. In this article, for the first time, the process technology for the phase change memory cell and array fabricated using SST as phase change material replacing conventional GST is presented. By adopting SST PVD process and confined structure, on a small-scale phase change memory array with CMOS access transistors and addressing circuit, we are able to fabricate and demonstrate its full function with low power. The cell electrical testing results are compared between two kinds of films. We also proved a different phase transition mechanism with SST material.

Sb-rich Si-Sb-Te phase change materials with different Si contents were proposed and fabricated, and the role of Si and Sb in the Si-Sb-Te alloys was discussed. The resistance-temperature and retention properties of the Sb-rich Si-Sb-Te alloys were studied. Devices based on the Sb-rich Si-Sb-Te alloys were fabricated by a 0.18 μm CMOS technology and device properties were studied by pulsed mode resistance-voltage (R-V) measurements. Experimental results show that the crystallization temperature and data retention ability of the Sb-rich Si-Sb-Te alloys were obviously improved with increasing Si content, but the electrical properties degenerate if too much Si was added. Sb is helpful to promote the crystallization process, but excessive Sb decreases the thermal stability. So, in order to obtain practicable Sb-rich Si-Sb-Te phase change materials, suitable Si and Sb contents are required to balance the device performances between electrical switching property and thermal stability or data retention ability.