The proliferation of multimodal artificial intelligence in embedded systems poses significant challenges for accelerator design, primarily due to the inherent heterogeneity in both dataflows and operators. This heterogeneity induces architectural mismatches, thereby severely impacting energy efficiency and complicating the systematic evaluation of accelerators. Moreover, traditional energy evaluations, which lack effective selection and optimization guidance tailored to the accelerator-multimodal paradigm, are neither cost-effective nor productive. First, this work introduces a unified evaluation framework, which offers insights into the complex interplay between architectures and multimodal workloads, guiding architecture selection, optimization of DNN acceleration, and subsequent circuit design. It features two techniques: (1) a systematic accelerator classification paradigm that enables efficient screening, qualitative comparison, and shorter preliminary selection cycles; (2) a set of quantitative metrics, including our proposed storage allocation, designed to diagnose architectural strengths and weaknesses in processing multimodal data heterogeneity, thereby providing guidance for optimization. Second, applying our framework to a representative baseline architecture, we identify critical memory access inefficiencies and computational bottlenecks, particularly when executing Depthwise Convolution. Guided by this analysis, we propose a targeted architectural optimization named Activation-Weight Swap with Register Optimization (AWSwap-Reg). This strategy improves energy efficiency by exploiting a previously underutilized dimension of parallelism through reconfigurable memory pathways and integrated additional registers. RTL-level simulations show that AWSwap-Reg reduces idle computation and memory energy consumption by 50% and 84%, respectively. These substantial gains are achieved with only a marginal overhead of approximately 6% in area and 1% in power, showcasing the efficacy of our framework-driven methodology.

For precision motion control systems, real-time feedforward compensation is indispensable, yet its implementation is constrained by latency, computational/storage hardware resources. Classic approaches, including online model-based feedforward and iterative learning control feedforward, fail to balance accuracy and generalization. Although offline neural network feedforward (NN-FF) has emerged as a potent alternative, in-depth investigation into its real-time deployment is still lacking. Furthermore, even state-of-the-art, offline recurrent NN-FF (RNN-FF) models impose substantial demands on hardware resources (due to large parameters and inherent sequential processing), making them less suitable for efficient real-time implementation. This paper proposes a generalized hardware-model co-optimization framework for real-time NN-FF. Specifically, we develop Motion Residual Convolution (MRC): a compact CNN-based model with high accuracy, strong generalization, lightweight design, and inherent parallelism for latency reduction. Correspondingly, we construct an accelerator core with 10 vector multiply-accumulate (VMAC) units for multi-filter parallel processing. For two scenarios with distinct priorities, specifically the resource-constrained and the latency-constrained, we adopt spatial feedforward acceleration engine (SFAE) and temporal feedforward acceleration engine (TFAE), respectively. SFAE maximizes throughput via independent VMAC arrays per convolutional layer, while TFAE optimizes resource utilization through time-multiplexing a single VMAC array across layers. Experiments indicate MRC outperforms RNN-based counterparts in accuracy, using <1% of their storage and computational resources. The proposed accelerators achieve high energy efficiency with compact hardware resources, benefiting from the lightweight MRC model. Moreover, both accelerators achieve effective trade-offs: compared with TFAE, SFAE consumes 6.9–40.9% more key logic resources and 3.1% more power but delivers an average 61× execution speedup, achieving an energy efficiency of 222.2 GOPS/W.

In modern intelligent wireless communication systems, the transmission configurations of radio frequency (RF) power amplifiers (PAs)-most notably transmit power- dynamically change across a wide range to accommodate various service scenarios and currently available communication resources, posing new challenges for digital predistortion (DPD). Traditional DPD solutions are primarily designed for scenarios where PAs operate at a constant average power level (PL) and thus cannot be directly applied, as the PA is a dynamic nonlinear system significantly influenced by PLs. To address this issue, a self-adaptive residual long short-term memory (SAR_LSTM) neural network (NN) is proposed in this article for wide dynamic power range quadrature switched-capacitor PAs (SCPAs). The proposed model adopts a two-stage approach comprising a power variation module (PVM) and a residual LSTM (R_LSTM). In the first stage, the PVM generates a power variation-dependent feature vector, which is then multiplied with the original input signal. In the second stage, the adjusted input signal passes through the R_LSTM to perform the corresponding predistortion calibration. This process tightly integrates the underlying causes of power variation in the SCPA circuit with our model, enabling highly accurate self-adaptive calibration across a wide dynamic power range without requiring parameter updates. In the measurement, a 15-bit transformer-based quadrature SCPA chip with Class-G and IQ-cell-sharing techniques is implemented in a 28-nm CMOS process and employed to verify our method. For the 802.11ax 40-MHz 64-QAM signal at 2.4 GHz, experimental results demonstrate that the proposed model achieves superior linearization performance compared with state-of-the-art (SOTA) models, with an average adjacent channel power ratio (ACPR) of -39.5 dB and an average error vector magnitude (EVM) of -41.6 dB over a 30-dB dynamic power range.

Near memory bank processing (NMBP) architecture only benefits memory-bound operations of DNNs in terms of energy consumption. Drawing on the insight that data compression can reduce the compute density of operators, transforming compute-bound operations into memory-bound operations, We propose CPSnB, a NMBP architecture combined with preserving numerical jump-spatial similarity compression (PNJ-SSC) method. CPSnB provides a tiling strategy for optimizing operators of different DNN models. Compared to the systolic host-side accelerator and existing dense and sparse NMBP, CPSnB significantly reduces energy consumption. Analysis of the experimental results indicates that a 60% compression ratio of activation can enhance the versatility of CPSnB in processing DNN operators to 22.3 times.

For the first time, this paper presents an unsupervised learning residual long short-term memory (ULR_LSTM) neural network to develop a digital predistortion (DPD) method for the linearization of digital power amplifiers (DPAs). Our method eliminates the need for iterative learning control (ILC) to obtain the ideal input of the DPA required by state-of-the-arts (SOTAs), which leads to high computational complexity and extensive training time. We perform behavioral modeling of the DPA using the R_LSTM network. After determining the optimal behavioral model architecture, the corresponding DPD model is obtained through an inverse training process. A 15-bit transformer-based quadrature DPA chip incorporating Class-G and IQ-cell-sharing techniques was implemented in a 28nm CMOS process to validate our proposed method. Experimental results demonstrate outstanding linearization performance comparing to prior arts, achieving an error vector magnitude (EVM) of -40.4dB for the 802.11ax 40MHz 64QAM signal.

For the first time, this paper proposes an attention long short-term memory (AT_LSTM) neural network to address digital predistortion (DPD) in digital power amplifiers (DPAs). This method first calculates the weights of different terms in the input sequence based on their contributions to the output using an attention module. Secondly, the weighted input sequence is used to construct and train the LSTM model. By applying the attention mechanism to the original input sequence to adjust weights, the LSTM model can selectively focus on key features, leading to a substantial reduction in parameter count while effectively addressing both static nonlinearity and memory effects in DPD. A 15-bit transformerbased quadrature DPA (QDPA) chip, integrating Class-G and IQcell-sharing techniques, was fabricated in a 28 nm CMOS process to validate the proposed method. Experimental results demonstrate that the proposed AT_LSTM model achieves superior linearization performance while using significantly fewer parameters and lower computational complexity than state-of-the-art (SOTA) models, with an error vector magnitude (EVM) of -40.3 dB for the 802.11ax 40 MHz 64-QAM signal at 2.4 GHz, thereby facilitating more energyefficient hardware implementations.

Deep neural networks (DNNs) predistortion models of radio frequency (RF) power amplifiers (PAs), while offering excellent performance, typically suffer from high parameter counts and computational complexity. Convolutional NNs (CNNs) have been introduced to reduce model complexity due to their weight-sharing characteristic. However, the inherent calculation mode of traditional convolutional structures limits their ability to effectively capture temporal dependencies within the data, hindering their effectiveness in addressing memory effects in PAs. In this letter, we propose an enhanced digital predistortion (DPD) model based on a real-valued residual temporal convolutional neural network (RVRTCNN) for quadrature digital PAs (QDPAs). The proposed model incorporates dilated convolutions to extract features across multiple time steps and capture complex temporal dependencies, thereby enhancing its ability to address the dynamic nonlinearity of PAs. A 15-bit transformer-based QDPA chip, integrating Class-G and IQ-cell-sharing techniques, was fabricated by 28 nm CMOS process to validate our proposed method. Experimental results demonstrate that the proposed model achieves superior linearization performance with significantly fewer parameters and lower computational complexity compared to state-of-the-art (SOTA) models, improving both adjacent channel power ratio (ACPR) and error vector magnitude (EVM) by over 10 dB for the 802.11ax 40 MHz 64-QAM signal.

Integrating compression in the multiply-and-accumulate (MAC) path can significantly improve the energy efficiency of DNN operators. However, existing unstructured sparse compression (USSC) methods struggle to effectively compress activations with low sparsity. Computing core processing USSC face challenges such as load imbalance and complex index control circuit design. Based on insights into local spatial correlation, a block-wise adaptive-pooling compression (APC) method is proposed to achieve a high compression ratio for activations. Furthermore, this paper proposes an APCPU to integrate APC into the MAC path with minimal overhead, facilitating highly energy-efficient sparse processing of DNN operators. Leveraging a hybrid data flow design to achieve load balancing results in speedups of 1.25x to 1.33x. The experiment results show that the APCPU achieves energy savings of 1.35x and 1.27x compared to JPZ-PU, and 2.63x and 2.71x compared to CSC-PU when evaluated on AlexNet and Bert.

The arithmetic intensity (ArI) of different DNNs can be opposite. This challenges the generality of single acceleration architectures, including both dedicated on-chip processing (OCP) and near-data processing (NDP). Neither architecture can simultaneously achieve optimal energy efficiency and performance for operators with opposite ArI. It is relatively straightforward to think of combining the respective advantages of OCP and NDP. However, few publications have addressed their real-time co-optimization, primarily due to the lack of a quantifiable offloading method. Here, we propose GPOS, a general and precise offloading strategy that supports high generality of DNN acceleration. GPOS comprehensively considers the complex interactions between OCP and NDP, including hardware configurations, dataflow (DF), DNN model, and interdie data movements (DMs). Three quantifiable indicators-ArI, execution cost (Ex-cost), and DM-cost-are employed to precisely evaluate the impacts of these interactions on energy and latency. GPOS adopts a four-step flow with progressive refinement: each of the first three steps focuses on a single indicator at the operator level, while the final step performs context-based calibration to address operator interdependencies and avoid offsetting NDP benefits. Narrowing down offloading candidates in step 1 and step 3 significantly accelerates real-time quantitative analysis. Optimized mapping techniques and NDP-input stationary DF are proposed to reduce Ex-cost and extend operator types supported by NDP. Next, for the first time, sparsity-one of the most popular methods for energy optimization that can alter data reuse or ArI-is quantitatively investigated for its impacts on offloading using GPOS. Our evaluations include representative DNNs, including GPT-2, Bert, RNN, CNN, and MLP. GPOS achieves the minimum energy and latency for each benchmark, with geometric mean speedups of 49.0% and 94.1%, and geometric mean energy savings of 45.8% and 89.2% over All-OCP and All-NDP, respectively. GPOS also reduces offloading analysis latency by a geometric mean of 92.7% compared to the evaluation that traverses each operator and its relative combinations. On average, sparsity further improves performance and energy efficiency by increasing the number of operators offloaded to NDP. However, for DNNs where all operators exhibit either very high or very low ArI, the number of offloaded operators remains unchanged, even after sparsity is applied.

Memory wall issue has become the overwhelming bottleneck of future systems due to the explosive parameter growth and low computing density large language model (LLM). Near-data processing (NDP) could alleviate data traffic and energy consumption, but the storage demand of LLM is still enormous. Weight sparsity is helpful for reducing data capacity. Unstructured sparsity sacrifices less accuracy compared to structured one, but the random non-zero values distribution in NDP leads to load imbalance among parallel processing units. Here we propose LauWS which is seamlessly combined into various prior arts of sparsity. LauWS follows the local characteristics of feature distribution in weight matrix for various models, preserving even tiny features and discarding non-feature values as far as possible region by region. That is the key for LauWS achieving a trade-off between high prune ratio (PR) and less accuracy loss (AL). Evaluations are carried out based on a GDDR6-based bank-NDP system. The typical optimization compared to the no-prune includes 38% speedup at 0.8PR with no AL for MLP, 22.7% speedup at 0.5PR with no AL for GPT-2, 23.6% speedup at 0.5PR with the lowest perplexity for OPT-125m.

Emerging embedded nonvolatile memory (eNVM) based on hafnium oxide ferroelectric materials has shown great advantages such as high reliability, high speed, good scalability, and CMOS process compatibility. Here, a 2T2C structure ferroelectric memory (FRAM) is proposed based on the 180-nm CMOS technology and a TiN/Hf $_{\text{0}.\text{5}}$ Zr $_{\text{0}.\text{5}}$ O $_{\text{2}}$ /TiN ferroelectric capacitor. The device exhibits great ferroelectric properties with the remnant polarization (2P $_{\text{r}}\text{)}$ of 30 $\mu$ C/cm $^{\text{2}}$ under a low operation voltage of 2 V. Also, it shows great high-temperature endurance and retention properties, which has no obvious degradation after 10 $^{\text{10}}$ cycles pulses and 10 $^{\text{4}}$ s under 175 $^{\circ}$ C. In addition, a 2-Mb capacity memory chip with 16 $\times$ 128 kb subarrays using the 2T2C structure and separated word lines (WLs) was fabricated. The wafer can maintain a high yield of 98.28% after baking for 30 h at 175 $^{\circ}$ C, which shows great reliability in the chip level.

Activation data size has been roaring with the development of convolutional neural networks, which accounts for the boosting storage requirements. Our insight indicates that non-zero values dominate activations, of which the patterns demonstrate near similarity. We propose ANS method to compress activations in real time during both training and inference. High compression ratio with less accuracy loss is achieved by our optimization strategies, including determination of selection box (SB) size according to the amount of zero values of layer, learning and calibrating threshold dynamically, using the mean value of similar SB as compression value. Over 49% of compression ratio is achieved with accuracy loss of less than 0.892%, as well as reduction of multiplications by more than 60%. Comparing to three state-of-art compressed methods under five mainstream CNN models, ANS provides compression ratio improvement of 3.2x over RLC5, 1.9x over GRLC and 1.7x over ZVC. The ANS compressor and decompressor are implemented in Verilog and synthesized in 28nm node, which indicates that ANS has less cost of performance and hardware overburden. ANS modules could be seamlessly attached at the interface or deeply coupled into DNN accelerator with changed data path in the MAC array, which achieve 38% and 56% reduction in energy consumption, respectively.

An on-chip digital sensor has been demonstrated in 28nm High-k Metal Gate (HKMG) for bias temperature instability (BTI) statistical characterization with the benefits: fast statistical measurement, less recovery impact (Toff-stress@around 15ns, Fast Period Sampling (FPS) @around 300ns), and high resolution (0.1mV of $\Delta $ Vth). As far as we know, it is the first time to statistically observe the very early stage of trap recovery of individual device in practical scenario, e.g., static random-access memory (SRAM). We find that three Negative BTI (NBTI) recovery behaviors, 2/3/4-step with clear transition slope, co-exist in HKMG devices. Our further analysis ascribes the phenomena to co-existing of four types of defects in 28nm HKMG Devices Under Test (DUTs). Three types are recoverable and one unrecoverable. The transition slope instead of steep drop between steps is the aggregative effects of one certain type of recoverable defect contained across DUTs. More types of defects lead to more Vth shift. But the contribution percentage of unrecoverable defect remains quite close, while recoverable defects dominate the Vth degradation. Only when the Toff-stress is less than the starting point of 1st recover step (within 1 $\mu \text{s}$ in our case), accurate and consistent Vth degradation data can be achieved.

Stannous oxide (SnO) and stannic oxide (SnO2) are both important wide-band-gap semiconductors. To study the conducive mechanism in detail, high quality epitaxial films are essential. Here we propose a simple method to grow high quality epitaxial films of either stannous oxide or stannic oxide on an r-plane sapphire substrate by using pulsed laser deposition with a metallic tin target. The valence state of tin is controlled by tuning the oxygen pressure during the deposition procedure. Metal tin impurities and the transition phase of Sn3O4 are avoided and the growth windows from stannous oxide to stannic oxide are confirmed. For single-crystalline SnO epitaxial film, a rocking curve half-width of 0.22 degrees is obtained, which is better than the 0.46 degrees of that on a YSZ substrate. The minimum roughnesses achieved were 0.37 nm for the SnO2 epitaxial film and 0.84 nm for the SnO epitaxial film. The epitaxial relationship between SnO and the r-sapphire substrate was determined to be SnO [(1) over bar 1 0]//sapphire [(1) over bar 2 (1) over bar 0] and SnO [1 1 0]//sapphire [1 0 (1) over bar 1]. For SnO2, the epitaxial relation is SnO2 [0 1 0]//sapphire [(1) over bar 2 (1) over bar1 0] and SnO2 [(1) over bar 0 1]//sapphire [1 0 (1) over bar 1]. The band schematics, deduced by combined XPS valence band spectroscopy and optical transmittance spectroscopy, indicated p-type bands of SnO and n-type bands of SnO2. Raman spectroscopy is suggested to be a superior fingerprint of SnO single-crystalline quality, due to its greater sensitivity than X-ray diffraction.

Magnetoresistive random access memory (MRAM) suffers from low magnetoresistance ratio and serious variations in both low-resistance state (R-P) and high-resistance state (R-AP). The resulting narrow resistance window between R-P and R-AP makes it difficult to acquire a sufficient sense margin for accurate read operation. In this brief, a novel read circuit forMRAMis proposed with dynamic data-dependent reference current to improve the sense margin. Instead of using the average of read currents of a pair of dummy R-P and R-AP cells as reference, our reference current is generated in a data-dependent manner by subtracting the read current of the selected cell from the sum of read currents of a pair of dummy R-P and R-AP cells. Thus, a larger or smaller reference current can be obtained for the read of R-AP or R-P cell, respectively, helping in expanding the sense margins. The larger sense margin can further improve the sense speed and the read yield. Evaluation shows that 2x increase in typical sense margin, 60% reduction in sense time, and remarkable reduction in bit error rate are achieved compared with the conventional averaging reference scheme. The accompanying cost in power consumption is acceptable.

Resistive random access memory (ReRAM) is very attractive for dense storage in embedded applications because of its good scalability and logic-process compatibility. However, ReRAM suffers from severe variations in R-off/R-on, endurance and retention, which greatly impair its yield and limit its application. Besides the variation sources from material defects, device non-uniformity and manufacturing deviations, circuit inability to provide an ideal write condition also plays an important role in causing above-mentioned variations. Especially, the requirement for a uniform and small overshoot compliance current during set (forming) is critical for narrowing the low-resistance state (LRS), i.e. R-on distribution, while the prior works fail to satisfy. This paper proposed a write driver with dynamic uniform and small overshoot compliance current under different set/forming voltages. The benefits of self-adaptive write mode (SAWM) are also reserved for both set and reset operations. Simulation shows that the compliance current with 5% variation for PVT variations and 3% overshoot is achieved.

A true random number generator using write speed variation of oxide-based RRAM is proposed for the first time. The signal of this physical unclonable function (PUF) is strong with long duration to be easily and accurately captured by simple circuit, of which the advantage is attributed to the mechanism that the speed variation amplifies the fluctuation of oxygen vacancy trap and de-trap. Some function parts of normal RRAM IP can be reused as entropy source cells and implementation circuit. The variation of write end point is monitored by a self-adaptive write drive circuit to trig a counter, and then serialized into a bit stream. The test chips, which are AlOx/WOx bilayer back-end RRAM fabricated in 0.18 Um logic process, passed all NIST tests with advantages of small area, low power, and not using post-processor corrector. Enough bits can be generated within the endurance limitation to ensure usual Internet of Things (IoT) security application.

Domain wall memory (DMW) or Racetrack memory (RM) has attracted great attention for its enormous capacity. However, the array architecture are not clear. Prior arts have very low capacity utilization (only 50%) as well as high shift voltage. This paper proposed a 1 transistor X cells (1TXC) array architecture based on X-bar cell structure for 3D DWM, which realizes 100% capacity utilization, 50% shift power reduction and attains simplified peripheral decoding circuit as well as cost efficiency. Further, a corresponding anti-disturbance read operation algorithm is put forward, which can inhibit misread problem caused by sneaking current.