Integrated dc-dc power converters have been the subject of intense research interest over the past 10 – 12 years because they offer so many potential benefits, not just in promising savings of up 20% of board space, but also enabling control of individual chip voltages and delivering power at high voltage and low current, thus reducing power train I 2 R loss. Among the various power converter options, the inductive Buck converter is the most attractive because it can deliver a wide output voltage range with an expected high efficiency (≥ 90%). However, for on-chip applications, the inductive Buck converter is the least developed power converter, there being at present no such inductor ready for use in a standard CMOS back-end-of-line (BEOL) fabrication facility. Major strides towards the realization of on-chip power conversion have been made by IBM in case of its POWER8 TM processor (1), and by Intel in case of its 4th generation (Haswell) processor (2), which uses near-chip- integrated power converters; although neither company’s new power converter used an integrated magnetic inductor. After highlighting the important role that magnetic inductors are expected to play in on-chip power conversion, this talk will describe new developments in magnetic materials for inductors, especially those employed at IBM, and the fabrication challenges faced in integrating these materials in inductors. Yoke material and thickness (typically 1 - 5 microns) can be tailored to reach desired inductance values (i.e., 1 – 30 nH) in thin-film ferromagnetic inductors, while endeavoring to maintain a high enough operating frequency (i.e., 20 – 200 MHz). Electrodeposition was an enabling technology for the thin-film magnetic recording head, and was thus used for yoke fabrication of our earlier inductors (3, 4). IBM and Columbia University recently demonstrated an efficiency of 82% in a World's first 3D-integrated inductor/voltage regulator that employed thru-silicon via technology and electrodeposited Ni 45 Fe 55 yokes (5). Nevertheless, significant advancements in eddy current suppression through electrodeposition of either sufficiently resistive or insulating-layer-laminated magnetic layers have proved elusive. Thus, considerable efforts have gone into developing new, higher resistivity, sputtered magnetic alloys (> 100 µΩcm), usually with insulating lamination layers. A notable example produced by sputtering is amorphous Co 91.5 Zr 4 Ta 4.5 (CZT), which has, for example, been used as the yoke material in inductors fabricated on top of 90 nm CMOS structures by Gardner et al. (6). We chose to explore sputtered, laminated, amorphous Co 20 Fe 60 B 20 magnetic films due to their extremely soft magnetic soft properties (Hc ≤ 0.1 Oe) and low, magnetic-permeability-related, loss tangent (≤ 0.1) for a wide range of frequencies, and thermal stability up to 350 o C. This required development of a new fabrication scheme to integrate the blanket-deposited, sputtered magnetic layers with 200 mm CMOS substrates. We employed ion beam etching (IBE) patterning methods since no other method, e.g., wet etching, could anisotropically etch all of the inductor yoke stack materials. Peak quality factors (Q) ≥ 12 (at 120MHz) were demonstrated on magnetic inductors containing laminated Co 20 Fe 60 B 20 magnetic films as shown in Fig. 1, double the Q values of previous inductors that had electrodeposited Ni 45 Fe 55 . All inductor devices functioned across a 200 mm wafer, the consistent device performance observed indicative of a reliable, high-yield fabrication process. Fig. 1. Left: Comparison of Q values for inductors with sputtered Co 20 Fe 60 B 20 materials and electrodeposited Ni 45 Fe 55 (for the latter, see ref. 3). Right: Summary of Q peak values for single-turn inductors on a 200 mm wafer. [1] Z. Toprak-Deniz et al., ISSCC Digest, 112 (2014). [2] E. A. Burton, et al., Proc. Applied Power Electronics and Expositions (IEEE-APEC), p. 432-439 (2014) [3] N. Wang et al., J. Appl. Phys., 111, 07E732 (2012). [4] N. Sturcken et al., ISSCC, 48, 244 (2013). [5] K. Tien et al., in VLSI Technology (VLSI technology), 2015 Symposium on, Kyoto, 2015, pp.C192-C193. [6] D. S. Gardner et al., J. Appl. Phys., 103, 07E927 (2008). Figure 1

Temporary wafer bonding and debonding techniques are becoming ubiquitous in the world of 2.5D and 3D technology. After a decade of research and development, two room-temperature debonding techniques have emerged as industry front-runners: laser-assisted debonding, and mechanical peeling, each having its particular strength. Mechanical debonding depends on proper engineering of the relative strengths of adhesion between the handler, the release layer, the adhesive and the device wafer. Once separation is initiated at a wafer edge, the handler is peeled away leaving the adhesive layer on the either the handler or the device wafer depending on the location of the release layer. Ultraviolet (UV) laser ablation using an excimer source in combination with an x-y scanning stage, or a solid-state laser paired with an optical scanner, has likewise been shown to be an effective debonding technique. In the case of laser-assisted debonding, questions arise as to the effectiveness of absorption in the material being ablated, the magnitude of the thermal pulse generated at the handler-release layer interface and its evolution as it transits the adhesive layer to reach the device wafer surface. In this paper, we apply time-dependent thermal finite element modeling to predict the duration of heating and maximum temperature excursion during the thermal evolution of the bonding structure including the silicon BEOL and device regions. The laser input is modeled as a distributed thermal pulse load determined by the input pulse energy, spatial distribution and laser absorption depth. We find that for optimized release layer, adhesive layer, laser wavelength and power level the majority of the heat flux flows into the handler wafer and heating of the device layers can be well below device limits. The effects of laser absorption depth in the release and adhesive layers, their thickness and material properties will be discussed.

Major strides in on-chip power conversion have been made by IBM in case of their POWER8TM processor (1), and by Intel in case of their 4th generation (Haswell) processor (2), although neither company’s new on-chip voltage regulator (VR) uses an integrated inductor. After outlining why on-chip power conversion is so desirable, this talk will highlight the important role of magnetic inductors in power conversion, and will review recent developments in, and prospects for, magnetic materials for inductors, especially those formed by plating methods. Granular DC-DC power delivery, consisting of fast dynamic voltage scaling for each load through use of a dedicated VR, can significantly improve energy efficiency. Traditionally, the large size of the inductor component has impeded efforts to fabricate the VR in one module. The preferred approach to shrinking the inductor is to increase the switching frequency. The downside to higher frequency operation is reduced efficiency and increased heat dissipation. Thus, shrinking the inductor involves a compromise of space vs. performance, and placing the VRM with an integrated inductor on the processor using thin-film fabrication processes is a natural, if challenging, progression. In thin-film ferromagnetic inductors, yoke material and thicknesses (typically 1 - 3 microns) can be tailored to reach desired inductance values (e.g., 10 – 40 nH), while endeavoring to maintain high enough operating frequency (e.g., 50 – 100 MHz). Considerable efforts have gone into developing new magnetic alloys with higher resistivity (> 100 µΩcm) to reduce yoke eddy currents. A notable example produced by sputtering is amorphous Co91.5Zr4Ta4.5 (CZT) [3, 4], which seems to have become the standard against which other materials are compared. This has been used as the yoke material in inductors fabricated on top of 90 nm CMOS structures by Gardner et al. [5], for example. Electroplating has been a standard technique for the deposition of thick metal films due to its high deposition rate, conformal coverage and low cost. It was an enabling technology for the thin-film magnetic recording head, and was thus used for yoke fabrication for our inductors (6, 7). For the latter, Ni45Fe55 was chosen over Ni80Fe20 for its higher magnetic moment (1.6T), high anisotropy field, and higher electrical resistivity (40 µΩcm). Plated Co-based materials are attractive alternatives to Ni-Fe as yoke materials, e.g. due to their higher moment, especially if their resistivity can be made to approach or exceed 100 µΩcm. We are exploring the use of electrolessly-plated, Co-W-P films for inductor applications (8). The electroless Co-W-P films show excellent magnetic properties, with good magnetic anisotropy, and coercivity of less than 0.1 Oe (Fig. 1). The resistivity of the films is about 90-100 µΩcm, which is close to that of most amorphous Co-based alloys. [1] Z. Toprak-Deniz et al., ISSCC Digest, 112 (2014). [2] E. A. Burton, et al., Proc. Applied Power Electronics and Expositions (IEEE-APEC), p. 432-439 (2014) [3] K. Hayashi et al., J. Appl. Phys., 61, 2983 (1987). [4] D. S. Gardner et al., IEEE Trans. Magn. 43, 2615 (2007). [5] D. S. Gardner et al., J. Appl. Phys., 103, 07E927 (2008). [6] N. Wang et al., J. Appl. Phys., 111, 07E732 (2012). [7] N. Sturcken et al., ISSCC, 48, 244 (2013). [8] N. Wang et al., MMM-Intermag, paper HG-11, 2013 Fig. 1. Hysteresis loop (left) and SEM Xsection (right) of an electrolessly-plated Co-W-P films. This work was supported in part by Lawrence Livermore National Laboratory subcontract No. B601996 under prime contract DE-AC52-07NA27344 from the U.S. Government. Inductor fabrication was carried out in the Microelectronics Research Laboratory (MRL) at IBM’s T. J. Watson Research Center.

An integrated voltage regulator (IVR) is presented that uses custom fabricated thin-film magnetic power inductors. The inductors are fabricated on a silicon interposer and integrated with a multi-phase buck converter IC by 2.5D chip stacking. Several inductor design variations have been fabricated and tested. The best performance has been achieved with a set of eight coupled inductors that each occupies 0.245 mm2 and provides 12.5 nH with 270 mΩ DC. With early inductor prototypes, the IVR efficiency for a 1.8 V:1.0 V conversion ratio peaks at 71% with FEOL current density of 10.8 A/mm2 and inductor current density of 1.53 A/mm2. At maximum load current, 69% conversion efficiency and 1.8 V:1.2 V conversion ratio the FEOL current density reaches 22.6 A/mm2 and inductor current density reaches 3.21 A/mm2.

Successful implementation of on-chip power conversion using ferromagnetic inductors requires both high power efficiency and high power density. The theoretical limits to power density and efficiency possible with thin film ferromagnetic inductors in a buck converter topology with and without coupling are explored. Power density can be related to energy density of the inductor, while efficiency can be related to Q and the DC resistance loss of the inductor. To achieve 100 A/cm2 for a 100 MHz 2:1 V converter with a 90% inductor efficiency, a peak Q of more than 8 is required with an energy storage of more than 5 nJ/mm2. Using coupling, the power density can be further increased, but is ultimately limited by DC resistance loss in the coils. Figures of merit (FOM) for comparing inductors of various designs are also discussed.

Thin-film ferromagnetic inductors show great potential as the energy storage element for integrated circuits containing on-chip power management. In order to achieve the high energy storage required for power management, on-chip inductors require relatively thick magnetic yoke materials (several microns or more), which can be readily deposited by electroplating through a photoresist mask as demonstrated in this paper, the yoke material of choice being Ni45Fe55, whose properties of relatively high moment and electrical resistivity make it an attractive model yoke material for inductors. Inductors were designed with a variety of yoke geometries, and included both single-turn and multi-turn coil designs, which were fabricated on 200 mm silicon wafers in a CMOS back-end-of-line (BEOL) facility. Each inductor consisted of electroplated copper coils enclosed by the electroplated Ni45Fe55 yokes; aspects of the fabrication of the inductors are discussed. Magnetic properties of the electroplated yoke materials are described, including high frequency permeability measurements. The inductance of 2-turn coil inductors, for example, was enhanced up to about 6 times over the air core equivalent, with an inductance density of 130 nH/mm2 being achieved. The resistance of these non-laminated inductors was relatively large at high frequency due to magnetic and eddy current losses but is expected to improve as the yoke material/structure is further optimized, making electroplated yoke-containing inductors attractive for dc-dc power converters.