Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties.

Using TCAD tools, many reliability issues can be studied quantitatively. Examples are hot carrier degradation of interfaces, threshold voltage shifts during NBTI stress, radiation effects and soft errors, ESD and latch-up, thermo-mechanical issues, electro-migration and stress-voiding.

The reliability of complex interconnect structures at all levels of the chip integration hierarchy has become a major concern due to the use of fine feature sizes, diverse materials, and complex 3D architectures. Reliability issues range from stress related failures such as dielectric cracking and interface debonding during manufacturing to electrical and mechanical failures such as electromigration and void formation during operation. This paper summarizes computational results obtained using a unified physics-based 3D simulation framework.

In this paper, we study the impacts of proximity effects on the electrical characteristics I-d-V-g and the static noise margin of a six-transistor (6T) bulk complementary metal-oxide-semiconductor (MOS) static random access memory (SRAM) cell using 3-D process and device technology computer-aided design (TCAD) simulations. We show that when a 6T SRAM cell is simulated as a single continuous 3-D structure, effective stresses in channels are reduced due to close proximity of n-channel and p-channel MOS transistors in the cell with respect to simulations of transistors as discrete 3-D structures. Furthermore, we find that doping in channels of SRAM transistors is reduced by well proximity and implant shadowing. Stress and doping proximity effects have opposite contributions to device performance. We estimate the influence of proximity effects for typical 32-nm technology to be more than 10% for certain electrical cell characteristics. We thus conclude that, to accurately predict electrical cell behavior via TCAD simulations, the 6T SRAM cell should be a single continuous 3-D structure, instead of a set of six discrete transistors, which are simulated as individual 3-D devices and connected via a netlist.

Shrinking feature sizes, novel device designs as well as stress engineering increase the need for three- dimensional process and device simulations. We present several application examples for full 3D process and device simulations using Sentaurus TCAD, including a 3D NMOSFET with shallow trench isolations (STI), a PMOSFET device with SiGe pockets for stress engineering (similar to the structure presented in Ref. [1]) and a Omega-FinFET (similar to structures presented in Refs. [2,3]). TCAD simulations of the full process flow as well as of the electrical device characteristics are performed. We also show examples of 3D oxidation simulations with Sentaurus Process.