This article introduces the use of through silicon vias (TSVs) connected to electrical switches as waveguides for wireless interconnects on 2.5-D interposer-based integrated circuits (ICs). The resulting wireless interconnect can be controlled at run-time with electrical switches on the TSVs forming the TSV-W(aveguide) (TSV-W). This run-time control allows for creating or blocking wireless interconnects based on the demands of the applications mapped to a multicore computing system. The 3-D finite element method (FEM) simulations of 2.5-D IC floorplans are utilized to demonstrate the utility of TSV-Ws when deployed with wireless interconnects built with TSV-A(ntenna)s (TSV-As). The wireless channel between two TSV-As at a communication distance of 15 mm, representative of distant cores on a $6\times 6$ multicore 2.5-D system, is improved from a 3.6-dB loss without proposed TSV-Ws to a stronger link with only a 2.6-dB loss with TSV-Ws ( $3.125\times $ improvement in bandwidth at −10 dB), primarily due to the directionality imposed by TSV-Ws. Also shown in FEM simulations is a configuration of an orthogonally bent wireless channel on a multicore 2.5-D IC system.

This paper introduces on-chip integrated rotary traveling wave oscillators (RTWOs) organized into rotary oscillator array (ROA) bricks as an external perturbation to induce subharmonic injection locking (SHIL) in oscillator-based Ising machines (OIMs). The implementation of SHILs on chip is challenging, as the frequency of SHILs must be multiples of the operating frequency of the OIM nodes, with on-chip variations affecting the phase, degrading the SHIL process. This impedes the scaling of OIM implementations, regardless of the topology of Ising nodes, coupling or graph mapping mechanisms. The ROA brick topology implementation of RTWOs generates high frequency signals that are shown to provide a stable 2.31 GHz SHIL signal under process, voltage, and temperature (PVT) variations. Under PVT variations, distributed ring oscillator-based SHILs (ROSC-SHIL) fail to perform injection locking while the proposed ROA brick-based SHIL (ROA-SHIL) preserve 93

Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100

This work presents a multi-stage coupled ring oscillator based Potts machine, designed with phase-shifted Sub-Harmonic-Injection-Locking (SHIL) to represent multivalued Potts spins at different solution stages with oscillator phases. The proposed Potts machine is able to solve a certain class of combinatorial optimization problems that natively require multivalued spins with a divide-and-conquer approach, facilitated through the alternating phase-shifted SHILs acting on the oscillators. The proposed architecture eliminates the need for any external intermediary mappings or usage of external memory, as the influence of SHIL allows oscillators to act as both memory and computation units. Planar 4-coloring problems of sizes up to 2116 nodes are mapped to the proposed architecture. Simulations demonstrate that the proposed Potts machine provides exact solutions for smaller problems (e.g. 49 nodes) and generates solutions reaching up to 97% accuracy for larger problems (e.g. 2116 nodes).

This work presents the utilization of rotary traveling wave oscillators (RTWOs) to implement an Ising machine. Ising machines utilizing ring oscillators have recently been demonstrated on silicon, for instance, for the solution of a max-cut problem. Rotary traveling wave oscillators scale better in frequency compared to ring oscillators, but have increased power consumption. Phase-based computing principles, implemented with the proposed RTWO-based Ising machines, are prime for high speed phase-based computation. The experiments reveal the proposed RTWO-based Ising machines provide significant reduction (5x) in runtime in the solution of the max-cut problem. The power dissipation is two orders of magnitude higher than the minuscule, low power ring-oscillators but RTWO-based Ising machines sub-linear increase with the demonstrated frequency increase from 2GHz to 32GHz for high speed phase-based computing. The accuracy of the solution is significantly improved as well, as demonstrated with respect to two of the D-Wave solvers (tabu and simulated annealing) acting as the baseline for ring oscillator and RTWO based Ising machines.

This paper introduces a novel design automation methodology for charge recovery logic (CRL). The proposed methodology combines a novel logic compression algorithm with automatic schematic generation to automate the design process of CRL, enabling power and performance simulations for a large number and variety of CRL circuits. As a measure of the effectiveness of the proposed design flow, automated implementations of CRL equivalents of the LGSynth’91 combinational benchmark circuits are compared with their CMOS counterparts. The results demonstrate a trade-off in power for area: Automatically generated CRL circuits dissipate 51.3% less power on average compared to CMOS equivalents, occupying 54.9% larger area.

This paper presents a coupled ring oscillator based Potts ma chine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, cap turing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines imple ments the Potts model with interacting spins represented by cou pled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3 coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the pro posed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes.

In this work, multiphase digital low-dropout (MP-DLDO) regulators are designed with resonant rotary clocks (ReRoCs) in order to improve on the tradeoff of conventional DLDOs between current efficiency and transient response speed. The proposed DLDOs are multiphased, coined MP-DLDOs, designed with a clock-gated control technique to provide high current efficiencies along with transient response improvements at GHz frequency levels. The multiple phases within the MP-DLDO are served with ReRoCs that provide: 1) a robust high-speed low-power resonant clock distribution solution for the synchronous elements in the multiphase DLDO architecture and 2) improve the transient response characteristics [dynamic voltage scaling (DVS) speed and voltage ripple] while saving power in the controller circuitry. The proposed MP-DLDOs are distributed across the chip to achieve low voltage ripple. SPICE simulations are performed on post-layout, parasitic-extracted models to evaluate the MP-DLDO architecture on open-source digital cores, with performance metrics that include the voltage ripple reduction, transient response speed improvement, and power savings in the control logic. The proposed MP-DLDO architecture, evaluated on an RISC-V design, demonstrates a DVS speed of 6.5 V/ $\mu \text{s}$ and an output voltage ripple of 21.1 mV (38% reduction when compared to a conventional DLDO) with a sampling frequency of 2 GHz.

Rotary traveling wave oscillators (RTWO) are designed to provide a high frequency clock signal through the silicon interposer to multiple chiplets in a heterogeneous 2.5D system. In particular, two different RTWO synchronization topologies are presented: 1) Active interposer RTWO and 2) passive interposer RTWO. The proposed topologies are evaluated across a silicon interposer with a dimension of 42 mm × 20 mm. Each topology is implemented with post-layout, parasitic extracted models for a clock frequency of ≈8 GHz. The performance metrics are presented for clock period, skew, rise time, fall time, and oscillation start-up and settling times across the multi-die system (MDS) with SPICE based simulations.

The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms propelled by applications, such as artificial intelligence, big data, and cybersecurity. The recent advances in technology to store digital data inside a deoxyribonucleic acid (DNA) strand, manipulate quantum bits (qubits), perform logical operations with photons, and perform computations inside memory systems are ushering in the era of emerging paradigms of DNA computing, quantum computing, optical computing, and in-memory computing. In an orthogonal direction, research on interconnect design using advanced electro-optic, wireless, and microfluidic technologies has shown promising solutions to the architectural limitations of traditional von-Neumann computers. In this article, experts present their comments on the role of interconnects in the emerging computing paradigms, and discuss the potential use of chiplet-based architectures for the heterogeneous integration of such technologies.

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

In this paper, a scalable and passive component-less power-clock generation for adiabatic logic circuits, inclusive of the adiabatic core, is presented. The power-clock is traditionally a sinusoidal signal, that acts as the power and timing source to adiabatic gates. The slope of the power-clock signal directly impacts the overall energy efficiency of the adiabatic gates. Prior works have considered using LC based power-clock generation circuits, which are often considered costly due to area and high-Q inductor requirements. In this paper, a scalable solution is presented that features a unique innovation for the power clock generation circuit in step-charged circuits designed with resonant clocking. In particular, resonant rotary style clocking is used to provide the low power control to step-charged power clock circuits. SPICE based simulations are performed at 400 MHz on large scale adiabatic implementations of LGSynth’91 benchmark circuits. The overall energy efficiency of the proposed implementations are compared to those of equivalent adiabatic circuits with a traditional LC power-clock solution.

On-chip wireless interconnects provide signal broadcasting and link shortcuts for improved latency and throughput, useful considering the increase of the number of processing elements on a chip. In this work, a through-silicon via antenna (TSV_A) for on-chip wireless communication is proposed. TSV_A significantly improves the wireless interconnect performance over current solutions of on-chip antennas, which occupy a large area of the chip and are not capable of far-reaching transmission. Printed circuit board (PCB) prototypes are designed and fabricated to validate the proposed TSV_A. The PCB prototype of the TSV_A has an insertion loss of 5–10 dB at a distance of ≃20 mm, measured in PCB and validated with high fidelity 3D finite element method simulation results. TSV_A has improved path loss, smaller size, and lower manufacturing costs due to the well-established TSV fabrication process for 3D-ICs. Projections for an on-chip 3D-IC operation indicate up to 40 dB improved signal strength compared to other on-chip antennas, with an insertion loss of ≃3–5 dB up to a 30 mm distance.

On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. This work challenges the on-chip antenna design conventions, and pushes toward a Through-Silicon Via-based antenna design called TSV_A that establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30mm on-chip distance. The TSV_A performance is evaluated in both Finite Element Method and system-level Network-on-Chip (NoC) simulations. A comparison to traditional wire-based NoCs, analysis of wireless multi-bands, and technology scaling to demonstrate the substantial area improvements compared to traditional wireless NoCs (up to 99.88%) are performed. Simulation results show an improvement in network latency up to similar to 13% (average improvement of similar to 7%), energy-delay improvements of similar to 34% on average, and an improvement in throughput up to similar to 34% (average improvement of similar to 23%), using Wireless NoC with multi-band TSV_As. The improved signal performance of TSV_A, and multi-band capabilities, are ideal for wireless intercell communication for programmable metasurfaces with dedicated communication layers.

The growing performance needs of modern data-driven applications related to the Internet-of-Things (IoT), Big Data, and Artificial Intelligence (AI) result in demand for increasingly higher levels of computational complexity, storage capacity, and communication performance in computing devices.Fast and efficient interconnects among processor cores and/or memory subsystems in high-end processing platforms have proven to be an expensive and elusive objective over more than a decade.Moreover, due to the rapidly growing deployment of computing devices across the globe, the total annual energy consumption for computing is projected to account for up to 20-25% of the annual primary energy consumption globally, by early in the next decade.Therefore, to meet the proliferating demands for computing without overshooting the global energy budget, scaling up the performance of the future computing systems with significant improvement in their energy-efficiency is of paramount importance.However, the computing industry will no longer be able to scale up computing capability and energy-efficiency using the basic approach of scaling down the transistor feature sizes or improving the bandwidth of conventional interconnection systems.To address this issue, significant research efforts have focused on design of novel and non-traditional interconnects.Recently, that effort is augmented and rivaled by the research on non-conventional or non-von Neumann architectures for computing.To unfold various aspects of the cutting-edge research in these unconventional paradigms of computing, especially to unpack what the impacts of these new paradigms of computing would be on the interconnection subsystems of future computing systems, we organized a panel entitled "Unconventional Computing and What It Means for the Future of Interconnects" as part of the IEEE/ACM International Workshop on Network-on-Chip Architectures (NoCArc) 2020.The following panelists participated in the panel, and they shed light on the topics of their respective expertise as listed below.

In this paper, the first comprehensive methodology is presented for design of low power adiabatic circuits inclusive of the adiabatic core design and the power-clock generation. Prior works have focused on either designing adiabatic cores or the power clock generation circuit, only. These non-comprehensive views can misrepresent the performance savings and fail to address the opportunities at integration. In this work, a comprehensive solution is presented that also features a unique innovation for the power clock generation circuit in step-charged circuits designed with rotary traveling wave oscillators (RTWO) and adiabatic frequency dividers. In experimentation, SPICE based simulations are performed at 416 MHz and 330 MHz in the 90 nm technology node and compared to CMOS based implementations, as well as other known power-clock generation techniques. A 32-bit CMOS adder consumes 3.5× more power when compared to the proposed 32-bit ECRL adder operating at a frequency of 416 MHz. Furthermore, 1000 32-bit CMOS adders in parallel consumes 3.4× more power when compared to 1000 32-bit ECRL adders in parallel designed with the proposed architecture at a frequency of 416 MHz.

In this work, we propose and evaluate a Network-on-Chip (NoC) augmented with light-weight processing elements to provide a lean dataflow-style system. We show that contemporary NoC routers can frequently experience long periods of idle time, with less than 10% link utilization in HPC applications. By repurposing the temporal and spatial slack of the NoC, the proposed platform, SnackNoC, is able to compute linear algebra kernels efficiently within the communication layer with minimal additional resource costs. SnackNoC 'Snack' application kernels are programmed with a producer-consumer data model that uses the NoC slack to store and transmit intermediate data between processing elements. SnackNoC is demonstrated in a multi-program environment that continually executes linear algebra kernels on the NoC simultaneously with chip multiprocessor (CMP) applications on the processor cores. Linear algebra kernels are computed up to 14.2x faster on SnackNoC compared to an Intel Haswell EPx86 processing core. The cost of executing 'snack' kernels in parallel to the CMP applications is a minimal runtime impact of 0.01% to 0.83% due to higher link utilization, and an uncore area overhead of 1.1%.

FinFET based, low swing clocking with rotary traveling wave oscillators (RTWO) is presented in this paper. It is shown that the low-swing clock signal generation by RTWOs is very effective, thanks to FinFETs accommodating high frequency operation and voltage scaling better than planar CMOS transistors. Low swing clocks are aimed at lowering the power dissipation of the clock networks, while maintaining the full voltage operation of non-clock components (such as logic and memory). In this work shows that robust low swing (LS) RTWOs are designed with FinFET based technologies. To this end, SPICE simulations are performed on the ISPD'10 clock benchmark circuits operating at 2.25GHz and 3GHz in the 16nm FinFET technology node. LS-RTWO based designs are compared to an all digital phase locked loop (ADPLL) based designs operating at the same target frequency. At 3GHz, the LS-RTWO consumes 36% lower power with 42:7 dB better phase noise @ 10MHz on comparison to corresponding ADPLL based designs.

On-chip wireless interconnects offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. The on-chip wireless interconnect field is a thriving research frontier, with small (in-package) and large (across server racks) scale innovations. This talk will review the primary focus and the supporting periphery being researched for on-chip wireless interconnects. For instance, the recent discovery of a through-silicon via antenna (TSV_A) will be highlighted for adaptability to a wide range of packaging medium that includes silicon-interposer based multichip packages. Projections of TSV_As indicate up to 40 dB improved signal strength compared to other on-chip antennas, with an insertion loss of 3-5 dB up to a 30 mm distance. The keynote will also highlight the old and new challenges that lie in the path to prominence, and the striking persistence of these challenges in remaining unsolved, despite the research frontier moving forward. A band of usual suspects, spread over a variety of simulation and measurement based studies, will be put to the test of time. The innovations from physical limitation of on-chip antennas to integration challenges at the system-level will be examined under the spotlight and the hindsight of a couple decades of research.

A novel flexible on-chip power and clock (FOPAC) generation and distribution circuit is proposed to enable fast dynamic voltage and frequency scaling (DVFS). FOPAC utilizes resonant rotary clocks (ReRoCs) along with multi-phase voltage regulators (MPVR) for the clock and power generation and distribution. The locally distributed ReRoCs provide the required clock phases to the MPVR, and the MPVR provides the required voltage levels to the ReRoC, providing spatial and temporal flexibility for fast DVFS. The ReRoC and MPVR share the on-chip fly capacitor of the switched capacitor voltage regulators to achieve greater frequency scaling at run-time while reducing the overhead. The FOPAC architecture is evaluated on industrial designs demonstrating a 2 ns DVFS switching time.