A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints.

In this paper, a novel local clock gate cluster-aware low voltage clock tree synthesis methodology is introduced. In low voltage/swing clocking, timing closure is a challenging problem due to tight skew and slew constraints. The clock gating makes this problem more challenging due to the high delay mismatch between the gated and the non-gated sinks. The proposed methodology preserves the power savings of the clock gating and exploits low swing clocking to further reduce the power consumption, while maintaining the same skew and slew constraints as the full swing counterpart. Experimental results performed on the large circuits of ISCAS'89 benchmarks operating at 1.5GHz in the 45nm technology node demonstrate that the proposed methodology can provide 38% power savings as compared to a full swing gated clock tree, achieving an additional 12% savings as compared to a low swing non-gated clock tree.

A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS'89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.

A slew-driven clock tree synthesis methodology, referred to as SLECTS, is proposed for clock networks operating at reduced voltages. SLECTS is developed to i) satisfy tight slew constraints, which might be highly challenging with skew-driven methodologies, particularly at scaled voltages, and ii) reduce the power dissipation of the clock tree, thanks to targeting slew and skew constraints methodically. SLECTS achieves up to 17% power savings compared to a traditional skew-driven methodology, at 3 GHz operation in a 20nm FinFET technology. Furthermore, SLECTS decreases the total buffer size of a large industrial circuit in 16nm FinFET technology by 59%, compared to an industrial vendor tool at similar clock skew and slew constraints.

Low swing/voltage clocking is a well-studied approach to reduce dynamic power consumption in clock networks. It is, however, challenging to maintain the same performance at scaled clock voltages due to timing degradation in the Enable paths that are required for clock gating, another highly popular method to reduce dynamic power. A useful skew methodology is proposed in this paper to increase the timing slack of the Enable paths when the clock network is operating at a lower swing voltage. The skew schedule is determined via linear programming. The methodology is evaluated on five largest IS-CAS' 89 benchmark circuits. The results demonstrate an average 47% increase in the timing slack of the Enable path, thereby facilitating low swing operation without degrading performance.

A low-swing clocking methodology is introduced to achieve low-power operation at 20nm FinFET technology. Low-swing clock trees are used in existing methodologies in order to decrease the dynamic power consumption in a trade-off for 3 issues: (1) the effect of leakage power consumption, which is becoming more dominant when the process scales sub-32nm; (2) the increase in insertion delay, resulting in a high clock skew; and (3) the difficulty in driving the existing DFF sinks with a low-swing clock signal without a timing violation. In this article, a FinFET-based low-swing clocking methodology is introduced to preserve the dynamic power savings of low-swing clocking while minimizing these three negative effects, facilitated through an efficient use of FinFET technology. At scaled performance constraints, the proposed methodology at 20nm FinFET leads to 42% total power savings (clock network+DFF) compared to a FinFET-based full-swing counterpart at the same frequency (3 GHz), thanks to the dynamic power savings of low-swing clocking and 3% power savings compared to a CMOS-based low-swing implementation running at the half frequency (1.5 GHz), thanks to the leakage power savings of FinFET technology.

A low swing clocking methodology applicable to industrial ICs and design flows is proposed. The proposed methodology consists of (1) a novel flip-flop cell that enables low swing operation at the sinks without degrading timing performance, (2) a new clock tree synthesis algorithm to satisfy the original skew/slew constraints within a voltage scaled clock network, and (3) skew scheduling method to fix possible timing violations in a gated, low swing clock network. Experimental results on ISCAS’89 benchmark circuits designed with a 45 nm technology demonstrate 37% and 22% reduction in, respectively, clock tree and flip-flop power consumption while satisfying the original timing constraints (i.e. same clock frequency, skew and slew) of the full swing clock network.

Low swing clocking is a well known technique to reduce dynamic power consumption of a clock network. A novel static D flip-flop topology is proposed that can reliably operate with a low swing clock signal (down to 50% of the VDD) despite the full swing data and output signals. The proposed topology enables low swing signals within the entire clock network, thereby maximizing the power saved by low swing operation. The proposed flip-flop is compared with existing low swing flip-flops using a 45 nm technology node at a clock frequency of 1.5 GHz. The results demonstrate an average reduction of 38.1% and 44.4% in, respectively, power consumption and power-delay product. The sensitivity of each circuit to clock swing is investigated. The robustness of the proposed topology is also demonstrated by ensuring reliable operation at various process, voltage, and temperature corners.

Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily gated clock networks where a local clock tree exists between clock gating cells and registers. A methodology is proposed in this paper to efficiently achieve clock skew scheduling in circuits with gated clock networks. The methodology is implemented via both linear programming and constraint graph based approaches, and evaluated using the largest ISCAS'89 benchmark circuits with clock gating. The results demonstrate up to approximately 21% reduction in clock period while maintaining the power savings achieved by clock gating. A conventional design flow is used for the experiments, demonstrating the applicability of the proposed algorithms to automation.

A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay product (PDP) for each level shifter is analyzed and compared. Worst-case corner analysis is performed for transient power, delay, and leakage power. The dependence of power and delay on input supply voltage level is also investigated for each topology. Simulation results demonstrate 43% and 36% reduction in, respectively, transient power and leakage power as compared to cross-coupled level shifter, while consuming 9.5% and 79.5% less physical area than, respectively, cross-coupled and bootstrapping techniques.

Low swing clocking is a low power design methodology that scales the clock voltage to decrease power consumption of the clock distribution networks, with an expected degradation in the performance. In this work, a novel low swing clock tree synthesis methodology is combined with a custom low swing clock-aware D flip-flop (DFF) design. The low swing clocking serves to reduce the power dissipation whereas the custom low swing-aware DFF serves to preserve the performance of the IC. The experimental results performed on the three largest circuits of ISCAS'89 benchmarks operating at 1GHz in the 32nm technology show that the proposed methodology can achieve an average of 16% power savings in the clock tree compared to its full swing counterpart, while satisfying the same clock skew (50ps) and slew (150ps) constraints at the worst case corner of operation. Moreover, the clock-to-output delay of the low swing DFF does not increase compared to traditional full swing DFF, while consuming only 1% more power.

This paper presents a new methodology that implements a low swing clock tree. For low power IC design, low swing clock trees are one of the known techniques to lower the overall power dissipation through decreasing the power consumption of the clock network, while trading off the clock skew, local timing (slack) and the variation-tolerance (due to decreased noise margin). In this paper, an iterative skew minimization scheme for low swing clock trees is proposed via in-place buffer sizing considering multiple process corners. The proposed approach can preserve the power savings of the low swing clock tree implementation across multiple process corners. The effect of the decreased clock swing on the local timing is analyzed: The degradation in the timing slack is shown to be insignificant due to bounded clock slew eliminating most of the timing degradation on the clock network or the logic paths induced by decreased clock swing. The experimental results show that the proposed methodology can achieve an average of up to 11% power savings, with a skew degradation of less than 5% compared to the original full-swing clock tree, satisfying a practical skew budget. The proposed scheme is highly practical as it only performs in-place buffer sizing on the original clock tree.

It is formidable to embed iterative simulations into the clock tree synthesis process to verify the skew and slew constraints. Instead, accurate and simple timing models for clock buffers are traditionally used so as to perform clock tree synthesis with sufficient accuracy. Two-pole RC and/or piecewise linear models accurately models the gate delay without a waveform dependency for a wide range of waveform properties. However, they unnecessarily complicate the problem for the time modeling of clock buffers where, unlike logic gates, the input and output waveform properties are similar. Look-up table-based approaches are traditionally used in order to obtain the clock buffer timing with inputs being the input slew and the output capacitance. However, the effective capacitance estimation of the highly resistive wires of sub-45nm technologies is a challenge, making it hard to identify the output capacitance. Also, the multiple or dynamically-scaled voltage levels of the current designs necessitate a costly LUT-based pre-characterization process. In this work, a timing estimation scheme for clock buffers is proposed which models both the delay and the slew as linear equations, bypassing the costly LUT characterization process. The experimental results performed with SAED 32nm buffer library show that the proposed timing model can achieve a maximum absolute value error of ≈5ps to ≈10ps for the buffer timing compared to SPICE simulations. Furthermore, the proposed timing model provides an error from 0.2% to 4.6% at different timing constraints and operating voltage levels, when used for insertion delay computation.

This paper introduces a methodology that optimizes the performance of a low swing clock tree under a skew bound. Low-swing clock trees are preferred for a reduction in the clock switching power, with an expected trade-off in clock slew and skew. In this paper, a heuristic optimization process is introduced that keeps the clock skew under the same skew budget of the originating full-swing clock tree. In this low swing clock optimization, the low power consumption property is preserved. The effect of slew on the logic timing, which is naturally degraded due to low-swing operation, is analyzed within timing slack of some paths in order to highlight the effectiveness of the low swing clock trees in lowering power consumption with limited impact on timing constraints. The experiments performed with the 4 largest ISCAS'89 benchmark circuits operating at 500~MHz, 90~nm technology and 4 different Vdd levels show that the optimized low swing clock tree can achieve an average of upto 11.0% reduction in the power consumption with no more than a skew degradation of 0.5% of the clock period (i.e. within the practical skew budget).

The development of a microcontroller-based system design course using the PSoC Lab Manual and customly designed project assignments are presented in this paper. Due to the natural segregation of computing blocks on these devices as digital vs. analog blocks, microcontroller-based systems can be taught in 2 terms, for digital and analog systems design separately. The presented course is designed to combine analog and digital design concepts in one single course that lasts for 10 weeks, using the PSoC3 board. The course is designed to include (i) lab tasks and (ii) weekly assignments. Based on the course syllabus, the students are assigned lab tasks following a selected lab from the PSoC3 Lab Manual each week. In addition to these selected labs from the manual, a weekly design project is assigned which cumulatively covers concepts both the current and previous weeks, in order to provide students in-depth knowledge about the microcontrollers and programmable system-on-chip boards.

This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh — each voltage domain requires a separate mesh. These disjoint meshes need to be matched in clock skew between the domains. In addition, the additional power dissipation of the level shifters in the logic needs to be compared against the power savings of multi-voltage domain implementation. The case study performed with the largest ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology concludes two important results that highlight the benefits of multi-voltage clock mesh design: 1) The multi-voltage domain clock mesh can achieve 37.14% lower power with a 9 ps increase in clock skew over the single-voltage domain clock mesh, and 2) The multi-voltage domain clock mesh achieves 66 ps less skew with a 20.92% increase in power dissipation over a multi-voltage domain clock tree.