3D NAND has become the mainstream technology to support bit growth of NAND Flash. The main challenge of 3D NAND is the increased level of wafer deformation as more layers are stacked vertically. This global deformation of the substrate leads to a significant degradation of overlay performance. One potential way to address this challenge is through bow compensation by wafer backside deposition. However, it turns out that standard backside processes sometimes do not improve overlay. This study investigates this phenomenon and explores how to counter high levels of wafer deformation in a way that overlay performance does not deteriorate. Scanner monitor wafers with etched reference marks have been modified to create a variety of global warp levels, covering a wafer bow range from +300 mu m (bowl shape) to -550 mu m (umbrella shape). Subsequently, several different backside deposition processes have been applied to these wafers. Flat reference wafers, warped wafers, and compensated wafers have been then measured on NXT scanners with different wafer tables. Non-linear overlay residuals of these wafers from about 1nm (flat reference wafers) to more than 30nm (uncompensated highly deformed wafers) have been measured. The obtained data reveal clear correlations between overlay, global wafer shape and backside deposition. A demonstration of the optimized overlay performance on wafers with large warpage values will be shown with a detailed analysis through absolute overlay metrology.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR (R) PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B (TM) EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex (TM) dielectric etch and Kiyo (R) conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.