Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR (R) PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B (TM) EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex (TM) dielectric etch and Kiyo (R) conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Vacuum ultraviolet (VUV) is investigated for removing single-wafer clean-related charging. Very short exposure time, within 10 s, successfully removed both positive and negative charging created by the single-wafer wet clean process. Comparing to results from other wavelength and past studies, an electron-hole pair excitement mechanism is proposed to explain the VUV charging removal of embedded charging in SiO2 films. The proposed mechanism raised a concern for film damage. Oxide capacitance/voltage (CV) curves and MOS capacitor oxide leakage currents are measured. CV curves showed a negative impact from VUV, but MOS capacitors can tolerate short VUV exposure times. The positive and negative impacts from VUV exposure are discussed.

Abstract Wafer charging becomes an increasingly important issue, thus being a key parameter in 10 nm and sub-10 nm technology nodes. Single-wafer cleaning equipment has various advantages over batch-type processes, and adoption has been widespread in both BEOL and FEOL manufacturing. Since the process module is constructed primarily of plastic for chemical compatibility, there are significant challenges in managing charge build-up to an acceptable level. Amongst known charging failure modes, an arcing event is the most destructive toward device yield. Hagimoto, Matz, and Halladay discovered that cleaning chemistries with different conductivity and film stacks generate different types of punch-through defects on the wafer surface. Dielectric layers such as SiO2 and Si3N4 are where these charges accumulate. Typically these charges could be dissipated by Ionized CO2 Water (DI-CO2) [4, 5, 6]. However, 10 nm BEOL processes have a very tight specification on Cu film loss, limiting the use of DI-CO2. Hayashi et al. reported that dilute NH4OH has lower Cu etch rate than does DI-CO2and also has high discharge capability [7]. In this study, a different approach is investigated. A vacuum ultraviolet (VUV) lamp is used to dissipate charge generated in a de-ionized water (DIW) single-wafer clean process. Experimental A VUV lamp (wavelength ~200-nm) is used on wafer discharging. 1,000 Å thermal oxide wafers were processed with DIW-only at 200 rpm, 60s, and 1 lpm flow with center dispense. Charging profiles were measured on a Qcept metrology tool. Results Figure 1 shows the effect of VUV discharging. The solid lines represent typical wafer charging by a DIW process. The thermal oxide wafer is negatively charged at the center. This is because of DIW tribo-electric charging effects from the DIW dispense at the center of the wafer. At the wafer edge, the process generates positive charge. The mechanism is correlated with the center-negative charging. When Si-OH at the center is negatively charged, H+ ions are generated; these spin out from the wafer center and accumulate at the wafer edge. In Figure 1a, the VUV lamp is located at the wafer center, and the post-VUV exposure charging profile is changed from -10V to 0V (broken lines). In Figure 1b, the VUV lamp is located at the wafer edge, and it also shows from +4V to 0V discharging. Two sets of data suggest that VUV can neutralize both positive and negative charges. In order to understand if there is any negative impact of VUV exposure, k-value shift of the dielectric film is measured. In Table 1, k-values are compared for different wafer locations – center, middle, and edge. The VUV nozzle is scanned from center to edge. The results are normalized to reference data with no VUV exposure. The center area showed a severe k-value shift with prolonged exposure time. This means that optimized exposure is needed to minimize damage due to VUV. Additional damage studies and optimized VUV scan profile will be introduced in the conference. (a) (b) Fig. 1: VUV discharge effects: (a) wafer center-negative charges are dissipated, (b) wafer edge-positive charges are dissipated. Table 1: Low-k film k-value shift after VUV exposure. By zone VUV 10s (normalized) VUV 120s (normalized) VUV 600s (normalized) Center 1.19 1.35 1.91 Middle 1.03 1.06 1.08 Edge 1.02 1.03 1.01 References [1] D. S. L. Mui, E. H. Lenz, C. Cyterski, K. Venkataraman and M. Kawaguchi, IEEE Transactions on Semiconductor Manufacturing., 24, Issue 4 (2011), 552. [2] Y. Hagimoto, H. Iwamoto, Y. Honobe, T. Fukunaga and H. Abe. Solid State Phenomena, 145-146, (2009), 112. [3] M. Wada, T. Sueto, H. Takahashi, N. Hayashi and A. Eitoku, Solid State Phenomena, 134, (2008), 263. [4] T. Guo, T. Tsai, C. Chien, M. Chan, C. Yang and J. Wu, Solid State Phenomena, 187, (2012), 63. [5] J. Halladay, B. Teeter, R. Newcomb, W. Usry, J. Yoo, K. Lam, J. Lansford and B. Brennan, Proceedings of SPCC08, Austin, TX, April (2008). [6] P Matz, T. Hurd, K. Cunningham et al., Proceedingsof the 212th ECS meeting, 7-10 October, (2007). [7] Y. Hayashi, M. Kawakami, D. Yano and K. Yamanaka, ECS Transactions, 69 (8), (2015), 37. Figure 1

A novel metallization scheme was developed to enable advanced BEOL interconnect scaling. The proposed approach adopts electroless Co to selectively grow Co in vias, followed by conventional Cu metallization for the trench. We have demonstrated the feasibility of this approach through the process integration of electroless Co via pre-fill on a two metal layer interconnect test structure. A detailed discussion on the yield improvement, parametric data, and reliability will be presented in this paper.

One of the main challenges facing the integration of metals as gate electrodes in advanced MOS devices is control over the Fermi level position at the metal/dielectric interface. In this study, we demonstrate the ability to tune the effective work function (EWF) of W-based electrodes by process modifications of the atomic layer deposited (ALD) films. Tungsten carbo-nitrides (WCxNy) films were deposited via plasma-enhanced and/or thermal ALD processes using organometallic precursors. The process modifications enabled us to control the stoichiometry of the WCxNy films. Deposition in hydrogen plasma (without nitrogen based reactant) resulted in a stoichiometry of WC0.4 with primarily W-C chemical bonding, as determined by x-ray photoelectron spectroscopy. These films yielded a relatively low EWF of 4.2 ± 0.1 eV. The introduction of nitrogen based reactant to the plasma or the thermal ALD deposition resulted in a stoichiometry of WC0.1N0.6–0.8 with predominantly W-N chemical bonding. These films produced a high EWF of 4.7 ± 0.1 eV.

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.