As technology nodes further shrink, high yield becomes more and more challenging to achieve. Photoresist resolution (see Figure 2) and CD uniformity are two core yield limiters. This can be improved with the use of Lam's EUV dry photoresist system([1]), where the dry develop technique is used to replace wet develop. This process is also less prone to pattern collapse([1]). Another advantage of this new photoresist system consists in its higher dose sensitivity compared to conventional photoresists which leads to higher throughput([1][2]). High resolution process needs to be combined with optical proximity correction (OPC) to enable cutting edge EUV patterning. OPC relies on the capability of a model to predict accurately the behavior of such an innovative process. The purpose of this study is to provide a comprehensive quantification and characterization of the accuracy of an OPC model fitted for this process ADI and AEI (after carbon open). We generated wafers exposed with an OPC calibration reticle, processed with Lam's dry deposited and dry developed photoresist. The anchor is a horizontal line-space grating at pitch 32nm (Figure 2). We acquired CDSEM images of more than 1800 features ADI (after dry develop) and AEI (after carbon open). A subset of the features were collected through FEM ADI. To better understand the characteristics of the dry photoresist system, we used metrics such as proximity, MEEF, DoF and EL. ADI OPC models were calibrated using ASML Tachyon software. Finally, we evaluated the OPC model accuracy of both Tachyon FEM+ (physically motivated) and Newron (machine-learning) engines, ADI for pitch 32nm BEOL metal layer use case.

Dual monopole exposure has been proposed1 as a way to improve imaging performance in EUV lithography by reducing the loss of contrast from image fading caused by the image shifts for the two poles of a dipole source. Simulations showed that the imaging advantages can be significant, with more than 15% image contrast improvements predicted. This paper presents experimental wafer data to demonstrate and verify the predicted advantages. The observed imaging enhancements include: • 18% better NILS (Normalized Image Log-Slope) for 28nm pitch patterns. • Better tip-to-tip patterns enabling gaps as much as 3nm smaller than normal patterning. Tip-to-tip LCDU and exposure latitude were improved at the same time, for better overall T2T capability. • Best focus offsets between three pitches: P28, P56 and P96 was reduced from 30nm range to nearly zero. • Smaller LWR (Line-Width Roughness), as much as 20% depending on pitch. • Reduced micro-bridging defects in the "stochastic cliffs" of narrow trenches, as large as a 40X defect density reduction for narrow trenches with 82nm pitch. Our experimental results validate the substantial imaging advantages seen by initial simulations. In addition to verifying dual monopole imaging advantages, our experiments have measured the pole-to-pole image shift δxP2P, an important parameter relating to image contrast which has never been measured before. This important parameter depends on the detailed mask structure as well as the specific shape and location of the source poles. Our measured δxP2P was consistent with simulated expectations.

Despite being crucial in an optical lithography process, “dose” has remained a relative concept in the computational lithography regime. It usually takes the form of a percentage deviation from a pre-identified “nominal condition” under the same illumination shape. Dose comparison between different illumination shapes has never been rigorously defined and modeled in numerical simulation to date. On the other hand, the exposure-limited nature of EUV lithography throughput demands the * illumination shape being optimized with the physical dose impact consciously taken into consideration. When the projection pupil is significantly obscured (as in the ASML EXE high NA scanner series), the lack of a proper physical dose constraint may lead to suboptimal energy utilization during exposure. In this paper, we demonstrate a method to accurately model the physical dose in an optical lithography process. The resultant dose concept remains meaningful in the context of a changing illumination pupil, which enables co-optimization of imaging quality and a throughput metric during the Source-Mask Optimization (SMO) phase, known as the Dose-Aware SMO. With a few realistic test cases we demonstrate the capability of Dose-Aware SMO in terms of improving EUV throughput via reducing the effective exposure time, in both regular and obscured projection systems. The physical dose modeling capability in computational lithography not only addresses those immediate challenges emergent from EUV throughput, but also opens the gate towards a broad class of exciting topics that are built upon physical dose, such as optical stochastic phenomena and so on.

Background: Contact hole variability is an important problem in the application of extreme ultraviolet lithography for memory applications. One method to reduce it is source optimization. An important source of on-wafer variability is the variability on mask. This can transfer in very different ways for different illumination pupils. Aim: Understand root cause of pupil-dependency of mask variability transfer to wafer. Predict which source can best reduce it. Approach: Look at the background diffraction intensity (BGI) caused by mask variability to explain aerial image LCDU. We make predictions of wafer LCDU based on how BGI transfers for different pupils and compare it to experimental data. Results: BGI has a spectrum that is given by the shape of the contact hole and is mostly concentrated at small spatial frequencies. For large sigma pupils much less BGI is transferred through the lens than for small sigma pupils. On wafer LCDU is well predicted by BGI divided by NILS. Conclusions: Large sigma pupils transfer much less BGI than small sigma pupils, so they reduce LCDU on wafer. For relaxed pitches, small sigma pupils can increase NILS by capturing additional diffraction orders of the periodic pattern. This can outweigh the larger BGI transferred and lead to smaller systematic LCDU for small sigma pupils. For high-NA, the central obscuration reduces BGI for small sigma pupils but large sigma pupils are still preferred. Tachyon SO can find the right pupils to minimize systematic LCDU by adding a large supercell clip with mask LCDU into the optimization.

In order to improve logic via printing we propose staggered vias to effectively regularize randomly placed vias in a typical logic design. We accomplish this (i) by forcing via placement on a staggered sub-grid of the standard manhattan grid and (ii) by placing smaller fixed-size via Sub-Resolution Assist Features (SRAFs) on all remaining empty positions of the staggered grid. We devised a methodology to create such staggered via placement in a standard Place&Route (PNR) design flow and evaluated the concept on a 64-bit (64b) ARM core implementation through a Power-Performance-Area (PPA) analysis. From a PNR run-time perspective and PPA analysis this looked a very viable implementation with little to no disadvantages compared to standard via placement. Finally, to experimentally test and compare staggered vias and against standard manhattan vias, we designed a via mask with both staggered and standard manhattan vias patterns and exposed them on an 0.33NA NXE3400 EUV lithography system. Analysis of experimental results on a 38nm via pitch show 40% smaller best-focus shift across the slit, and 20% smaller via-via CD variation for staggered vias compared to Manhattan vias with regular SMO.

Extending 0.33 NA extreme ultraviolet single patterning to 28-nm pitch becomes challenging in stochastic defectivity, which demands high-contrast lithographic images. The low-n attenuated phase-shift mask (attPSM) can provide superior solutions for individual pitches by mitigating mask three-dimensional effects. The simulation and experiment results have shown substantial imaging improvements: higher depth of focus at similar normalized image log slope and smaller telecentricity error values than the best binary mask configuration. In this work, the exploration of low-n attPSM patterning opportunity for pitch 28-nm metal design is investigated. Using generic building block features, the lithographic performance of the low-n attPSM is compared with the standard binary Ta-based absorber mask. In addition, the impact of mask tone (bright field (BF) versus dark field) on the pattern fidelity and process window is evaluated both by simulations and experiments. The results indicate that BF low-n attPSM provides the best patterning performance. Consequently, the BF low-n attPSM patterning performance is assessed with an actual imec N3 pitch 28-nm random logic metal design. The wafer data indicate BF low-n attPSM enables good patterning fidelity, as well as good overall process window with high exposure latitude (similar to 20 % ). (c) 2022 Society of Photo-Optical InstrumentationEngineers (SPIE)

In this work we studied the impact of stochastic resist defects on electrical measurements of BEOL structures, and seek to demonstrate that large electrical test structures, built with a relatively simple patterning flow, can be used in the early stages of resist, and patterning development, as the electrical failures are almost exclusively caused by resist defects. To that end, single-layer electrically testable metal patterns at minimum metal pitch of 28nm were created using a single 0.33NA-EUV exposure and a metal damascene process flow. A bright field mask was exposed with a metal-organic, negative-tonedevelopment resist process to create trench structures that are transferred into an oxide dielectric layer. Following this, the trenches were filled with ruthenium (Ru) for electrical testing of meander resistor and fork-fork structures.

As technology nodes shrink, OPC model accuracy needs to the fulfill tighter requirements. Those requirements can be met only under good process control. However, OPC model accuracy relies on the specific context. Ignoring the impact of process variation on OPC accuracy could lead to break edge placement error (EPE) budget. The OPC process monitoring project at imec is conducted on imec logic N7 M2 design at pitch 32nm use case and aims at quantifying long-term validity of the OPC model in the face of NXE:3400 scanner and process variations. To account and compensate for scanner and process variations impact, the ability of restoring OPC validity by OPC model dose tuning is tested.

We evaluated the printability of patterns relevant for Logic Metal at P28nm (L/S and T2T) on wafer using EUV single expose. We compare illumination sources with and without fading correction as well as Bright field / Dark field mask tonalities and NTD MOR / PTD CAR resist. In simulations, Bright field (BF) imaging gives better image quality than Dark field (DF) at small pitch/CD. It also enables smaller T2T. To avoid tone inversion (assuming dual damascene processing), BF imaging requires the use of a NTD resist. On wafer, exposure latitudes increase for a BF/NTD choice, concurrent with simulations, even after correcting out SEM shrinkage. Also, T2T CD is reduced. In terms of illumination, we compare dipole sources to fading corrected sources. As fading correction, we have both induced aberrations (Z6-corrected dipole) and monopoles. As expected, a fading correction significantly reduces best focus differences of L/S through pitch and T2T. Moreover, the Z6-corrected dipole is optimal to print small T2T with better uniformity. Finally, we observe that PTD and NTD MOR resist utilize the same aerial image differently. NTD resist can leverage pupil shapes with high exposure latitude, but low depth of focus, better than PTD resist. Fading correction via induced aberrations naturally produces such sources. In summary, the preferred option is a Z6-corrected dipole for best focus alignment and sharp T2T, together with BF imaging to allow higher L/S exposure latitudes and small T2T. Combining this choice with NTD MOR resist avoids tone inversion and leverages the illumination source optimally.

In this contribution we describe a simulation and experimental study investigating the impact of mask non-ideality and Mask Process Correction (MPC) model choices on Optical Proximity Correction (OPC) model accuracy for an EUV use case. We describe simulation flows and their results for two cases. In the first case we investigate the impact of using an MPC simulated mask contour vs an ideal post-OPC mask. In the second case we investigate the differences between simulations using experimentally measured and simulated mask contours. The wafer data used in this study is an N5 M2 process developed at IMEC with contour-based metrology performed using ASML MXP. NCS NDE-MPC models are created using POR CDSEM CD data and MXP contour data. OPC models are calibrated and evaluated using ASML FEM+ software.

Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is > 100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR (R) PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B (TM) EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex (TM) dielectric etch and Kiyo (R) conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

Both local variability and optical proximity correction (OPC) errors are big contributors to the edge placement error (EPE) budget which is closely related to the device yield. The post-litho contact hole healing will be demonstrated to meet after-etch local variability specifications using a low dose, 30mJ/cm2 dose-to-size, positive tone developed (PTD) resist with relevant throughput in high volume manufacturing (HVM). The total local variability of the node 5nm (N5) contact holes will be characterized in terms of local CD uniformity (LCDU), local placement error (LPE), and contact edge roughness (CER) using a statistical methodology. The CD healing process has complex etch proximity effects, so the OPC prediction accuracy is challenging to meet EPE requirements for the N5. Thus, the prediction accuracy of an after-etch model will be investigated and discussed using ASML Tachyon OPC model.

Inpria has developed a directly patternable metal oxide hard-mask as a high-resolution photoresist for EUV lithography(1). In this contribution, we describe a Tachyon 2D OPC full-chip model for an Inpria resist as applied to an N7 BEOL block mask application.

In the course of assessing OPC compact modeling capabilities and future requirements, we chose to investigate the interface between CD-SEM metrology methods and OPC modeling in some detail. Two linked observations motivated our study: 1) OPC modeling is, in principle, agnostic of metrology methods and best practice implementation. 2) Metrology teams across the industry use a wide variety of equipment, hardware settings, and image/data analysis methods to generate the large volumes of CD-SEM measurement data that are required for OPC in advanced technology nodes. Initial analyses led to the conclusion that many independent best practice metrology choices based on systematic study as well as accumulated institutional knowledge and experience can be reasonably made. Furthermore, these choices can result in substantial variations in measurement of otherwise identical model calibration and verification patterns. We will describe several experimental 2D test cases (i.e., metal, via/cut layers) that examine how systematic changes in metrology practice impact both the metrology data itself and the resulting full chip compact model behavior. Assessment of specific methodology choices will include: • CD-SEM hardware configurations and settings: these may range from SEM beam conditions (voltage, current, etc.,) to magnification, to frame integration optimizations that balance signal-to-noise vs. resist damage. • Image and measurement optimization: these may include choice of smoothing filters for noise suppression, threshold settings, etc. • Pattern measurement methodologies: these may include sampling strategies, CD- and contour- based approaches, and various strategies to optimize the measurement of complex 2D shapes. In addition, we will present conceptual frameworks and experimental methods that allow practitioners of OPC metrology to assess impacts of metrology best practice choices on model behavior. Finally, we will also assess requirements posed by node scaling on OPC model accuracy, and evaluate potential consequences for CD-SEM metrology capabilities and practices.

Process-window (PW) evaluation is critical to assess the lithography process quality and limitations. Usual CD-based PW gives only a partial answer. Simulations such as Tachyon LMC (Lithography Manufacturability Check) can efficiently overcome this limitation by analyzing the entire predicted resist contours. But so far experimental measurements did not allow such flexibility. This paper shows an innovative experimental flow, which allows the user to directly validate LMC results across PW for a select group of reference patterns, thereby overcoming the limitations found in the traditional CD-based PW analysis. To evaluate the process window on wafer more accurately, we take advantage of design based metrology and extract experimental contours from the CD-SEM measurements. Then we implement an area metric to quantify the area coverage of the experimental contours with respect to the intended ones, using a defined "sectorization" for the logic structures. This 'sectorization' aims to differentiate specific areas on the logic structures being analyzed, such as corners, line-ends, short and long lines. This way, a complete evaluation of the information contained in each CD-SEM picture is performed, without having to discard any information. This solution doesn't look at the area coverage of an entire feature, but uses a 'sectorization' to differentiate specific feature areas such as corners, line-ends, short and long lines, and thus look at those area coverages. An assessment of resist model/OPC quality/process quality at sub nm-level accuracy is rendered possible.

While waiting for EUV lithography to become ready for adoption, we need to create designs compatible with both EUV single exposures as well as with 193i multiple splits strategy for technology nodes 7nm and below needed to keep the scaling trend intact. However, the standard approach of designing standard cells in two-dimensional directions is no more valid owing to insufficient resolution of 193-i scanner. Therefore, we propose a standard cell design methodology, which exploits purely one-dimensional interconnect.

The image border is a pattern free dark area around the die on the photomask serving as transition area between the parts of the mask that is shielded from the exposure light by the Reticle Masking (ReMa) blades and the die. When printing a die at dense spacing on an EUV scanner, the reflection from its image border overlaps with the edges of neighboring dies affecting CD and contrast in this area. This is related to the fact that EUV absorber stack has 1-3% reflectance for actinic light. For a 55nm thick absorber the induced CD drop at the edges is found to be 4-5 nm for 27 nm dense lines([1]). In this work we will show an overview of the absorber reflection impact on CD at the edge of the field across EUV scanner generations, for several imaging nodes and multiple absorber heights.Increasing spacing between dies on the wafer would prevent the unwanted exposure but results in an unacceptable loss of valuable wafer real estate thereby reducing the yield per wafer and is thus not a viable manufacturing solution. In order to mitigate the reflection from the image border one needs to create a so called black border. The most promising approach is removal of the absorber and the underlying multilayer down to the low reflective LTEM substrate by multilayer etching([6]). It was shown in the previous study([1]) that the impact on CD was reduced essentially for 27 nm dense lines exposed on ASML NXE:3100.In this work we will continue the study of a multilayer etched black border impact on imaging. In particular, 22 nm lines/spaces imaging on ASML NXE: 3300 EUV scanner will be investigated in the areas close to the black border as well as die to die effects. We will look closer into the CD uniformity impact by DUV Out-of-Band light reflected from black border and its mitigation. A possible OPC approach will also be evaluated.

Computational lithography has become indispensable when developing lithography solutions for advanced technology nodes. One of the essential instruments for optimizing full-chip process windows (PW) is source mask optimization (SMO). To avoid model calibration for each new optimized source, separable resist models need to be created such that a reliable model can be obtained simply by replacing the source in the existing OPC model. In this paper we start from a fully calibrated resist model and optimize a new source for which we want to create a reliable OPC model. Relying on the separability of the model, the initial illumination source is replaced by the new one while not changing any resist model parameters. In order to reach the accuracy needed for OPC, the best focus and best dose still need to be accurately determined. We will investigate two models that have the same new SMO source and original resist model. For one model the best focus and dose are determined by the simulated Bossung plot of one anchor feature. The second model’s best focus and exposure are determined by a small set of FEM experimental data. The quality of these two models is then evaluated by comparing them to a reference model, which is fully calibrated using a complete dataset for the new source. We show that the calibrated FEM OPC model can be extrapolated by simply changing the source. A limited amount of experimental FEM data is required to accurately determine the best focus and exposure for the new source. Best focus and exposure based on the anchor pattern simulation has a higher degree of uncertainty compared to a small set of experimental data.