Self-Aligned Quadruple Patterning (SAQP) is used in advanced CMOS-FET technologies to enable the formation of arrays of fins at sub-40 nm pitches. As these technology nodes keep scaling down and the fins get taller for performance improvement, the patterns become denser and present very high aspect ratio (HAR). The scaling trends make the fin pattern more subject to mechanical instabilities during the processing steps. We describe in this paper a specific mechanical fin bending mode linked to the SAQP scheme targeting 24 nm pitch, the HAR and the formation and recess steps of the isolating oxide. We investigated the evolution of fin bending throughout the fin and isolation formation. We observed fins start bending at the FCVD deposition step exhibiting rotation angles up to 3 degrees. The bending was then worsened along the subsequent process steps causing mechanical failure after fin reveal where up to 7-8 of bending angles were observed. After having studied the influence of the key process steps, we can report a path to mitigate this phenomenon. Finally, we propose a simple mechanical analysis to validate quantitatively the root cause and extrapolate the mechanical robustness of this system for further scaling nodes where fin pitch is reduced.

A novel metallization scheme was developed to enable advanced BEOL interconnect scaling. The proposed approach adopts electroless Co to selectively grow Co in vias, followed by conventional Cu metallization for the trench. We have demonstrated the feasibility of this approach through the process integration of electroless Co via pre-fill on a two metal layer interconnect test structure. A detailed discussion on the yield improvement, parametric data, and reliability will be presented in this paper.

The Fin-FET Technology scaling to sub 7nm node, using 193 immersion scanner is restricted due to reduced margins for process. The cost of the process and complexity of designs is increasing due to multi-patterning to achieve area scaling using 193i scanner. In this paper, we propose a two Fin-cut mask design for Fin-pattering of 112 SRAM (two Fins for pulldown and one Fin for pull-up and pass-gate device) cell using 193i lithography and its comparison with EUVL single print. We also propose two keep masks for middle of line patterning, with increased height of the SRAM cell using 193i, that results in area of a uniform-Fin SRAM cell area at 7nm technology; whereas EUVL can enable non-uniform SRAM cell at reduced area. Due to unidirectional patterning, margins for VIA0 landing over MOL are drastically reduced at 42nm gate pitch and hence to improve margins, the orientation for 1 st metal is proposed to be orthogonal to the gate. This results in improved performance for SRAM and reliability of the technology.

An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechanical planarization (CMP) and dry etching steps. The process combines two steps on a single-wafer platform: (1) bulk Si etching chemistry with high etch rate (>10 μm/min.) to replace the CMP or polishing and (2) selective Si etching chemistry (Si: SiO 2 ~ 1800:1) to replace the Si recess dry etching step. Using this process, Si thickness uniformity can be significantly improved (for 20 μm Si removal), resulting in a lower variation in step height of through-Si via (TSV) protrusion across a 300 mm wafer. The overall cost is significantly lower than CMP plus dry etching. After the integrated wet etching process, passivation layers of low-temperature silicon nitride and oxide were deposited on the backside, followed by CMP to planarize the wafer and expose the Cu nails. The film adhesion is very good without showing any film delamination or peeling. This new integration scheme is robust with a wide process margin and provides cost savings over the conventional BVR flow.

One of the main challenges facing the integration of metals as gate electrodes in advanced MOS devices is control over the Fermi level position at the metal/dielectric interface. In this study, we demonstrate the ability to tune the effective work function (EWF) of W-based electrodes by process modifications of the atomic layer deposited (ALD) films. Tungsten carbo-nitrides (WCxNy) films were deposited via plasma-enhanced and/or thermal ALD processes using organometallic precursors. The process modifications enabled us to control the stoichiometry of the WCxNy films. Deposition in hydrogen plasma (without nitrogen based reactant) resulted in a stoichiometry of WC0.4 with primarily W-C chemical bonding, as determined by x-ray photoelectron spectroscopy. These films yielded a relatively low EWF of 4.2 ± 0.1 eV. The introduction of nitrogen based reactant to the plasma or the thermal ALD deposition resulted in a stoichiometry of WC0.1N0.6–0.8 with predominantly W-N chemical bonding. These films produced a high EWF of 4.7 ± 0.1 eV.

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.

An improvement in interconnect performance implies a reduction of the resistance–capacitance (RC) time constant. Instead of scaling the capacitance at each technology node through a reduction in the dielectric constant of the interlayer dielectric (ILD), the interconnect aspect ratios could be scaled holding the ILD fixed. In this case, the material properties of the ILD must be robust to process-induced damage and amenable to the creation of high aspect ratio features. In addition, a metallization scheme that can provide void free Cu fill in high aspect ratio features is required. Characterization, patterning, and integration results collected on such an ultra-low-k (ULK) ILD material and void free metallization is presented. A measured reduction in the resistance of a 22nm node interconnect in this ILD was observed as a function of increasing aspect ratio. The copper seed deposition process, capable of enabling the fill of even higher aspect ratio features, is also discussed.

Amorphous carbon hard mask films grown with plasma enhanced chemical vapor deposition are an enabling technology for advanced front-end-of-line patterning technologies. These films must have a low etch rate and be weakly roughened in dielectric etch chemistries, high transparency at lithography alignment wavelengths, and the mechanical properties to mitigate elastic instabilities such as line bending. The deposition process affects all of these parameters through the resulting structure and composition. Highly graphitic films deposited at 550°C are common; however, other process spaces relying on ion bombardment rather than temperature can create less graphitic films with improved film properties like transparency, hardness, and etch selectivity.

A high density/low resistivity TaN film grown using ion-induced atomic layer deposition (iALD) has been developed as the metal barrier for nano-scale Cu interconnects. Excellent conformalilty and Cu barrier performance enable the use of thin iALD TaN as the metal barrier. Integration of this film has demonstrated improvement in line and via resistance while maintaining robust electromigration (EM), via stress migration (VSM), and dielectric reliability performance.

A new process to promote adhesion between the SiC diffusion barrier and Cu was developed to achieve significant improvement in electromigration of the Cu interconnect without sacrificing RC delay, line-to-line leakage, breakdown voltage and time-dependent-dielectric-breakdown. An in-situ treatment of the wafer surface inserted between the sequential processes of Cu pretreatment and SiC deposition increased the Cu/SiC interfacial adhesion by more than 30%. Electrical and physical characterization data is presented that demonstrates the improvement in reliability metrics of the interconnect using the newly developed process, while limiting the RC change to <; 1%.

Electron scattering mechanisms in copper lines were investigated to understand the extendibility of copper interconnects when linewidth or thickness is less than the mean free path. Electron-beam lithography and a dual hard mask were used to produce interconnects with linewidths between 25 and 45 nm. Electron backscatter diffraction characterized grain structure. Temperature dependence of the line resistance determined resistivity, which was consistent with existing models for completely diffused surface scattering and line-edge roughness, with little contribution from grain boundary scattering. A simple analytical model was developed that describes resistivity from diffuse surface scattering and line-edge roughness.

Today's Through Silicon Via (TSV) processes are limited to aspect ratios of 10:1. High performance logic devices drive the need for aspect ratios approaching 20:1 in order to achieve the desired performance while simultaneously reducing costs. The reduced via area required on the wafer enables the designer to utilize less real estate on the die to reduce cost or to potentially add redundant vias to improve yield. However, current conventional processes and techniques are not capable of achieving robust fill on aspect ratios greater than 12:1. This presentation will highlight the technical challenges in achieving robust copper fill on super high aspect ratio TSV structures. Additionally, a compelling, economic solution pathway will be presented that integrates a low temperature conformal high quality dielectric isolation layer, a high step coverage Cu barrier / seed technology and a void free high speed electroplating process with a wide process window that could accelerate the adoption of the high aspect ratio TSV design schemes.