Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The quest for high-density, energy-efficient memories continues, with cryogenic memory solutions still unclear. We present a Cryogenic Capacitorless Random Access Memory (C2RAM) cell using advanced Si technology, which enhances storage density through its scalability and multistate capability. Remarkably, the C2RAM maintains data for over a decade with its extended retention times and offers potential as an artificial synapse. This positions C2RAM as an ideal nonvolatile memory candidate for cryogenic computing applications and emerging quantum technologies.

Large area PMOSFETs were characterized at room and cryogenic temperatures by admittance spectroscopy to determine transport parameters (e.g., hole mobility in the inversion layer). The devices were simulated in the linear response regime by an efficient drift-diffusion (DD) model including Fermi-Dirac statistics, band tailing and impurity freezeout that shows excellent numerical stability under cryogenic conditions. By inverse modeling accurate device models of the complex PMOSFETs were derived avoiding the stringent approximations of the analytical approaches. A high degree of consistency of simulations and measurements for the small-signal capacitance, conductance and drain current was obtained, by which the hole mobility extracted from the drain current could be verified by independent conductance measurements. In a next step the model could be used to extract data of interface states from measurements at 4.2 K, for which the usual methods based on MOS capacitors fail due to impurity freezeout.

Abstract In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functionality. We discuss source gated transistors, which allow for excellent electronic characteristics for low power, low frequency environmentally friendly circuits. We also consider reconfigurable field effect transistors. In such devices, two or more independent gate electrodes can be used to program different functionalities at the device level, enabling ultra-secure embedded devices. Both types of transistors can be used for neuromorphic systems, notably by combining them with ferroelectric SB transistors which enable a large number of analog states. At cryogenic temperatures SB transistors can advantageously serve for the control electronics in quantum computing devices. If the source/drain of the metallic contact becomes superconducting, Josephson junctions with a tunable phase can be realized for scalable quantum computing applications. Developing applications using SB devices requires physics-based and compact models that can be used for circuit simulations, which are also discussed. The roadmap reveals that the main challenges for these technologies are improving processing, access to industrial technologies and modeling tools for circuit simulations.

Herein, cryogenic field‐effect transistors (FETs) are discussed. In particular, the saturation of the subthreshold swing due to band tailing is studied. It is shown with simulations and experiments that engineering of the oxide‐channel interfaces and a strong increase of the gate oxide capacitance are effective in improving the switching behavior of the device. The implication of scaling the oxide capacitance on the power consumption of cryogenic devices is investigated, too. Furthermore, an alternative for conventional doping in cryogenic transistors is discussed. Based on synchrotron X‐Ray absorption spectroscopy at total fluorescence (XAS‐TFY) and ultraviolet photoemission spectroscopy (UPS) measurements, it is shown experimentally that in true nanoscale devices, a simple coating yields a shift of the conduction band that is equivalent to a very high dopant concentration. As a result, nanoscale cryogenic steep slope FETs with strongly improved electrical characteristics become feasible.

Abstract Efficient computing in cryogenic environments, encompassing classical von Neumann architectures, advanced quantum and neuromorphic systems, holds the potential to revolutionize big data processing. As the demand for high storage density and energy-efficient memories grows, the absence of a clear solution for cryogenic memory remains a challenge. Here, we present a cryogenic capacitorless Random Access Memory (C2RAM) utilizing advanced Si technology. This innovation is positioned to reshape cryogenic computing, with its high scalability and the capacity to be written and erased across multiple-states, significantly boosting the storage density. Notably, the C2RAM requires only ultra-low write energies, measuring just a few zeptojoules and provides exceptionally long retention times preserving data for over a decade. This positions C2RAM as a prime contender for nonvolatile memory for cryogenic von Neumann architectures and quantum technologies. In addition, the memory unit emulates biological synapses, including potentiation and depression, enabling a seamless integration into crossbar arrays, requiring no additional selectors for neuromorphic computing. The fusion of logic and analog capabilities unlocks substantial potential for high-density cryogenic memory applications. This innovative breakthrough enables the convergence of classical von Neumann, quantum, and neuromorphic computing, harnessing the significant performance advantages anticipated at cryogenic temperatures.

The performance of metal-oxide field-effect tran-sistors is studied at cryogenic temperatures. Several approaches to reduce disorder-induced band-tailing and thus improve the switching behavior of cryogenic MOSFETs are discussed.

Miniaturized electrolyte–insulator–semiconductor capacitors (EISCAPs) with ultrathin gate insulators have been studied in terms of their pH‐sensitive sensor characteristics: three different EISCAP systems consisting of Al–p‐Si–Ta 2 O 5 (5 nm), Al–p‐Si–Si 3 N 4 (1 or 2 nm)–Ta 2 O 5 (5 nm), and Al–p‐Si–SiO 2 (3.6 nm)–Ta 2 O 5 (5 nm) layer structures are characterized in buffer solution with different pH values by means of capacitance–voltage and constant capacitance method. The SiO 2 and Si 3 N 4 gate insulators are deposited by rapid thermal oxidation and rapid thermal nitridation, respectively, whereas the Ta 2 O 5 film is prepared by atomic layer deposition. All EISCAP systems have a clear pH response, favoring the stacked gate insulators SiO 2 –Ta 2 O 5 when considering the overall sensor characteristics, while the Si 3 N 4 (1 nm)–Ta 2 O 5 stack delivers the largest accumulation capacitance (due to the lower equivalent oxide thickness) and a higher steepness in the slope of the capacitance–voltage curve among the studied stacked gate insulator systems.

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SS th of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G m at 5.5 K.

The present paper studies with experiment and simulation a number of measures that improve current cryogenic MOSFETs to enable the device to be operated at very low supply voltages.

Problems with doping in nanoscale devices or low temperature applications are widely known. Our approach to replace the degenerate doping in source/drain (S/D)-contacts is silicon nitride interface engineering. We measured Schottky diodes and MOSFETs with very thin silicon nitride layers in between silicon and metal. Al/SiN/p-Si diodes show Fermi level depinning with increasing SiN thickness. The diode fabricated with rapid thermal nitridation at 900 ∘C reaches the theoretical value of the Schottky barrier to the conduction band ΦSB,n=0.2 eV. As a result, the contact resistivity decreases and the ambipolar behavior can be suppressed. Schottky barrier MOSFETs with depinned S/D-contacts consisting of a thin silicon nitride layer and contact metals with different work functions are fabricated to demonstrate unipolar behavior. We presented n-type behavior with Al and p-type behavior with Co on samples which only distinguish by the contact metal. Thus, the thermally grown SiN layers are a useful method suppress Fermi level pinning and enable reconfigurable contacts by choosing an appropriate metal.

We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the injection through a Schottky barrier. Operating the RFET in PGAS mode yields a switching behavior close to a conventional MOSFET. This, however, needs to be traded off against strongly nonlinear output characteristics for small bias voltages. Our measurement results are supported by transport simulations employing a nonequilibrium Green’s function approach.