One of the major challenges during recent years was to achieve the compatibility of III-V semiconductor epitaxy on silicon substrates to combine opto-electronics with high speed circuit technology. However, the growth of high quality epitaxial GaAs on Si is not straightforward due to the intrinsic differences in lattice parameters and thermal expansion coefficients of the two materials. Moreover, antiphase boundaries (APBs) appear that are disadvantageous for the fabrication of light emitting devices. Recently the successful fabrication of high quality germanium layers on exact (001) Si by chemical vapor deposition (CVD) was reported. Due to the germanium seed layer the lattice parameter is matched to the one of GaAs providing for excellent conditions for the subsequent GaAs growth. We have studied the material morphology of GaAs grown on Ge/Si PS using atomic layer epitaxy (ALE) at the interface between Ge and GaAs. We present results on the reduction of APBs and dislocation density on (001) Ge/Si PS when ALE is applied. The ALE allows the reduction of the residual dislocation density in the GaAs layers to 10 5 cm −2 (one order of magnitude as compared to the dislocation density of the Ge/Si PS). The optical properties are improved (ie. increased photoluminescence intensity). Using ALE, light emitting diodes based on strained InGaAs/GaAs quantum well as well as of In(Ga)As quantum dots on an exactly oriented (001) Ge/Si pseudo-substrate were fabricated and characterized.

Strained Silicon On Insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, this new technology potentially combines enhanced devices scalability allowed by thin films and enhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate by experimental results how a layer transfer technique such as the Smart Cut™ technology can be used to obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments and characterizations will be used to characterize these engineered substrates and show that they are compatible with the applications.

Effect of Silicon Surface Cleaning on the Initial Stage of Selective Titanium Silicide Chemical Vapor Deposition, K. Saito, T. Amazawa and Y. Arita, Jap. J. of Appl. Phys., 29 (1990) L185. Selective Titanium Silicide Chemical Vapor Deposition with Surface Cleaning by Silane and Ohmic ContactFormation to Very Shallow Junctions, K. Saito, T. Amazawa and Y. Arita, J. ElectrochemSoc., 140 (1993) 513. A comparative study of TiSi obtained by solid-state reac tion and chemical vapor deposition, P. Gouy-Pailler, M. Haond, D. Mathiot, M. Gauneau, A. Perio, and J.L. Regolini, Appl. Surf. Sci. 73 (1993) 25. US005633036A

We investigate in this work an original contact architecture to address 64 nm pitch transistor technology. This architecture, studied here in the fully-depleted silicon-on insulator (FDSOI) flavour, remains suitable for planar and 3D (trigate, FinFET) approaches. It includes a recessed gate-first process and self-aligned contacts that offer alternative solutions to technological problems such as limits in lithography resolution and stepper misalignment.Because this type of contact architecture is likely to increase parasitic coupling between gate and source/drain (S/D) contacts, a set of optimization rules is proposed based on numerical simulations. It is found that reducing gate thickness remains the best option to decrease the parasitic gate-to-S/D contact capacitance when transistors feature standard nitride spacers. The use of a low permittivity and thick gate capping layer is highly recommended to limit the sensitivity of parasitic capacitances to non-uniformity associated to chemical mechanical polishing (CMP) and stepper misalignment during S/D contacts lithography.When low-k spacers are considered, the same optimization rules are still relevant to further decrease parasitic capacitances at the transistor level. In the particular case of airgap spacers, they result in a 50% reduction of the total parasitic capacitance. Nevertheless, when used alone, low-k spacers can reduce parasitic coupling by up to 80%; they appear as a first order parameter to tune parasitic capacitances.At the circuit scale, it is demonstrated that an optimized architecture including low-k spacers is mandatory to meet the specific 10 nm node speed requirements at the circuit level. Insights are finally given to correctly choose the active area width Wand supply voltage V-DD taking into consideration the speed/power consumption trade-off. We particularly showed that if a voltage value lower than the nominal supply voltage is used, spacers optimization become even more effective to reach higher circuit speed at constant dynamic power consumption. (C) 2014 Elsevier Ltd. All rights reserved.

The outgassing of e-beam resist materials has to be carefully considered in the research and development of multi e-beams lithography. The release of hydrocarbonaceous species by outgassing in high-vacuum e-beam exposure tool is indeed unavoidable and may lead to premature contamination of optics projection systems. Such a contamination may affect the incident electrons path and hence the final imaging performances. In this work, we present an experimental methodology for the purpose of e-beam resist outgassing qualification. A specific experimental setup was designed in CEA-Leti in order to perform electron bombardment of the e-beam resists coated on 100 mm silicon wafers and to monitor the induced outgassing phenomena. The wafer stage was designed in order to allow suitable displacements of the resist coated surface with respect to the incident e-beam. In addition, the wafer can be exposed through specific silicon micromachined membranes (called mimic) that are representative of the optics projection system usually embedded in real multi e-beam exposure tools. Finally, a Quadrupole Mass Spectrometer (QMS) is plugged into the vacuum chamber and enables in situ analysis of the by-products outgassing. Combining this tool with the Thermo Desorption Gas Chromatography coupled to Mass Spectroscopy and Flame Ion Detector (TD/GC/MS-FID) analysis, we could not only determine the outgassing amount of four different resists but also identify all by-products outgassed and their origin. This paper also shows that the use of a thin top-coat can considerably reduce the outgassing. The outgassing amount as well as the top-coat efficiency was shown to be dependent on the resist chemical properties. Crown Copyright (C) 2013 Published by Elsevier B.V. All rights reserved.

We have studied oxidized porous silicon (OPS) properties using Fourier transform infraRed (FTIR) spectroscopy and capacitance–voltage C–V measurements. We report the first experimental determination of the optimum porosity allowing the elaboration of high-density OPS insulators. This is an important contribution to the research of thick integrated electrical insulators on porous silicon based on an optimized process ensuring dielectric quality (complete oxidation) and mechanical and chemical reliability (no residual pores or silicon crystallites). Through the measurement of the refractive indexes of the porous silicon (PS) layer before and after oxidation, one can determine the structural composition of the OPS material in silicon, air and silica. We have experimentally demonstrated that a porosity approaching 56% of the as-prepared PS layer is required to ensure a complete oxidation of PS without residual silicon crystallites and with minimum porosity. The effective dielectric constant values of OPS materials determined from capacitance–voltage C–V measurements are discussed and compared to FTIR results predictions.

This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

Silicon dioxide films deposited on InP substrates are obtained in a reduced pressure, air and water cooled horizontal CVD reactor, with a rapid thermal heating. Deposition temperature as high as 700°C could be utilized with no degradation of the InP surface. At this temperature the resulting silicon dioxide films have excellent structural and electrical properties. MIS capacitors fabricated on InP substrates have been tested and a transistor behaviour has been observed on a first set of InP MISFETs. In situ processing for surface preparation prior to deposition can be utilized with this technique. A first attempt of in situ multiprocessing was carried on silicon substrates and is presented here.

We have developed an electrochemical method allowing an accurate determination of doping profiles in p-type silicon. Our approach is based on a precise and reproducible measurement of the anodization potential during the formation of porous silicon. The technique is tested on a reference sample with staircase doping profile ranging from 1017 to 1019 cm−3. It is shown that the depth resolution is readily linked to the doping level. For high doping concentrations, it approaches that of the secondary ion mass spectroscopy analysis with an estimated value of 60 nm/decade.

Back surface passivation is one of the major challenges in the backside illuminated sensor technology. Ion implantation followed by non-melt pulsed Laser Thermal Annealing (LTA) has been identified as a promising candidate to address this issue. In this work, a shallow B-doped layer is implanted at the backside, further activated using LTA in the non-melt regime. LTA process effectiveness in terms of crystal damage recovery as well as dopant diffusion and activation is studied through room-temperature photoluminescence, Secondary Ion Mass Spectroscopy and four-point probe sheet resistance. These studies demonstrate that non-melt LTA with multiple pulses induces high activation without visible diffusion with an effective curing of the implantation-induced crystalline defects. This is made possible thanks to a submicrosecond process timescale coupled to a reasonable number of shots as shown by thermal simulations and simple diffusion estimations.

We have studied the porous silicon (PS) formation dependence on the substrate doping concentration as a selective tool to form locally oxidized regions in silicon wafers. This approach could be used for electrical isolation in CMOS circuits as a promising alternative to the shallow trench isolation STI process which begins to show some limitations (voiding and dishing) for the most advanced technologies.

In situ transmission electron microscopy (TEM) observations were performed for a better understanding of the “melt quenched” GeTe crystallization mechanism. The evolution of the crystallite morphology observed during annealing shows a growth-dominated crystallization behavior. Scanning transmission electron microscopy—electron dispersive x-ray spectroscopy and high resolution electron microscopy experiments were also performed on cycled GeTe devices, showing that void formation is responsible for the cell failure after 107 cycles.

Poly-SiGe stacked gates with Ge content ([Ge])varying between zero and 100% have been fabricated using an industriel single-wafer machine. These poly-SiGe layers were characterised and fully integrated in a 0.18 pm CMOS process. Interdiffusion of Si and Ge upon subsequent annealing of the structure has been observed and studied. This interdiffusion effect was found to be responsible for the discrepancy observed between theoretical and practical values of the Ge workfunction ϕms evaluated from our electrical measurements and from those of different authors. A technique for the limitation of this interdiffusion effect has then been developped and is described.

In this letter, we present a study on the electrical behavior of phase-change memories (PCMs) based on a GeTe active material. GeTe PCMs show, first, extremely rapid SET operation (yielding a gain of more than one decade in energy per bit with respect to standard GST PCMs), second, robust cycling, up to 1 × 105, with 30-ns SET and RESET stress time, and third, a better retention behavior at high temperature with respect to GST PCMs. These results, obtained on single cells, suggest GeTe as a promising alternative material to standard GST to improve PCM performance and reliability.

We have studied the oxidation of embedded SiGe mesas on SOI in order to co-integrate planar high Ge enriched mesas and Si mesas in the same wafer. We show that oxidation of such structure by local Ge condensation technique leads to non-uniform areas close to mesa sidewalls. Because oxidation kinetic seems to be lowered at a certain point, and since oxidation kinetic is assumed to be stress-dependent, we propose to act on the different sources of strain to counterbalance the difference in oxidation kinetic. In one hand, strain induced by the growth of SiO 2 is removed by alternation of SiGe oxidation and SiO 2 removal during the whole process. On the other hand, the nitride oxidation mask is deposited with compressive or tensile intrinsic stress to study its influence on the induced strain in the SiGe mesa. We show that by choosing the right value of intrinsic stress in the nitride, uniform SiGe mesa with high Ge content could be achieved.

We report material and electrical properties of tungsten silicide metal gate deposited on 12in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSix thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSix/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2nm, and a reduction of two decades in leakage current as compared to SiO2/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4eV which matches with the +0.2eV above Si midgap criterion for NMOS in ultra-thin body devices.

Advanced structures with poly-Si gates, Si3N4 spacers, and shallow trench isolation (STI) areas were used for elaborating the selective growth of Si1-yCy films into recessed source and drain (S/D).Selective Si1-yCy films were grown by repeated cycles consisting of two distinct steps: a non-selective CVD growth of Si1-yCy layers, and a chemical vapor etching with hydrochloric gas. This cyclic deposition/etching process has been experimented at 600 degrees C with a methylsilane/(methylsilane+trisilane+hydrogen) mass flow ratio (SiCH6 MFR) equal to 2.8 x 10(-4) used for Si0.99C0.01 film deposition. Regarding etching step, a pure HCl gas/(hydrogen) mass flow ratio (HCl MFR) was about 4.3 x 10(-1). We should note that the poly-crystalline Si1-yCy layers are etched more rapidly than the monocrystalline layers. The etching rate ratio between poly and mono areas induces the capability, by cyclic process, to remove the deposited poly-crystalline Si1-yCy layers on the dielectric areas (STI spacers) selectively versus the recessed mono-crystalline Si1-yCy layers. A global time process, of about 3 h, resulted in 50 nm thick Si0.99C0.01 films selectively grown into recessed S/D.The new TEM technique of dark-field holography was used to determine a mapping of the strain at transistor level (within Si channel among S/D);The tensile stress of about 0.2 GPa has been measured within Si channel (300 nm length) among recessed Si0.985C0.015 films. (C) 2009 Elsevier Ltd. All rights reserved.

We show that a significant enhancement of the direct band gap photoluminescence can be achieved at room temperature in bulk Ge and Ge-on-insulator heavily n-doped by gas immersion laser doping. The photoluminescence signal from bulk Ge and Ge-on-insulator increases with the donor concentration. An enhancement factor of 20 as compared to the undoped material is achieved near the 1550 nm wavelength for active dopant concentrations around 5×1019 cm−3. These results are supported by calculations of the Ge spontaneous emission spectrum taking into account the doping effect on the electron distribution in the direct and indirect conduction band valleys.