Next-generation BSI CMOS Imager Sensors are strongly driven by novel applications in depth sensing, mainly operating in the NIR (940nm) spectrum. As a result, the need for higher pixel sensitivity while shrinking pixel pitch is more present than ever. In this work, we present a new technology platform based on ad-hoc nano diffractor geometries, integrated in the Back Side of BSI CIS that allow to drastically improve the QE of the sensor for pitches varying from 10 μm down to 2.2 μm, co-optimized for both optical and electronic pixel performance.

In this paper we present a detailed performance status of AlGaN/GaN MOS channel High Electron Mobility Transistors (MOSc HEMTs) with fully recessed gate architecture on 200mm Si substrates. We report a wide range of wafer and package level results. ON state resistance is studied through three aspects: i) RON partitioning with analysis of its four components, ii) RON temperature dependence, iii) cumulative dynamic RON under stress. For accurate power assessment we characterize packaged devices and compare the typical figures of merit (gate charge, switching tests) to state of the art references (especially pGaN gate HEMTs). We highlight the benefits offered by this technology for 650V applications, such as very low I GSS leakage even at 150°C, and better switching performances, t d(on) , t d(off) .

A2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance. Even the device structure is not exactly what we expect, we succeed to evidence 1T-DRAM programming.

The impact of several wet etchants commonly encountered in the microelectronic industry on the surface chemistry of GaN on silicon was explored. In order to get closer to fully recessed gate HEMT fabrication processes, we investigated different kinds of GaN surfaces. This study was conducted on as-grown GaN and dry etched GaN, with etching consisting of inductive coupled plasma reactive ion etching (ICP-RIE), followed by atomic layer etching (ALE) and O2 plasma stripping. The impact of each wet treatment was evaluated by parallel Angle Resolved X-ray Photoelectron Spectroscopy (pAR-XPS). Treatment with phosphoric acid (H3PO4) showed a significant modification of the surface and further studies were performed using this treatment. The impact of H3PO4 on GaN surface chemistry and morphology was assessed by pAR-XPS and atomic force microscopy (AFM) respectively. A delayed effect was observed for dry etched samples compared to as-grown samples, with a successful recovery of the surface after 60 min of treatment. We also proposed a mechanism explaining the progressive formation on steps on the surface over time. Further research was performed on dry etched samples without ALE which also modified the delay time of the H3PO4 treatment, but still enabled a recovery of the surface morphology. In contrast to other studies, we showed that, with the appropriate choice of parameters for the H3PO4 treatment, it was possible to successfully recover the GaN surface after dry etching without significantly opening dislocation holes. This is therefore a promising treatment to be used during GaN HEMT processing to recover good quality surfaces after etching.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow w...

For the first time FDSOI CMOS transistors with Si-monocrystalline channel have been fabricated at a temperature below 500°C. High performance PMOS (Ion=450μA/μm (Vdd −0.9V) @ Ioff=2nA/μm Lg=35nm) with low overlap capacitance (0.46fF/μm per device), low gate resistance (10Ω) at Low Temperature (LT) enables to achieve good RF Figure-Of-Merit (FOM) with Fmax values up to 170GHz. In addition, we demonstrate for the first time the full functionality of Ring Oscillators (RO) and SRAM bitcells processed at 500°C, paving the way for a high-performance 3D sequential CMOS integration.

The efficiency of the “Siconi®” process, which is based on the use of a NH 3 / NF 3 remote plasma and anneals at temperatures less than 180°C, was recently assessed on SiGe surfaces. Siconi® removed GeO 2 and SiO 2 , but was less efficient on GeO x . The presence of residual GeO x after a Siconi® process was minimized with the use, beforehand, of a wet oxidation. It consisted on dips in Standard Cleaning 1 (SC1) solutions made of NH 4 OH, H 2 O 2 and H 2 O or in water with a few ppm of Ozone. A SiO 2 - rich oxide was generated, then (P.E. Raynal et al, Microelec. Eng. 187-188, 84 (2018)). In this study, we elaborate on those findings by comparing the performances of (i) wet, (ii) Siconi® and (iii) “wet - Siconi®” sequences on re-epitaxy on SiGe surfaces. Those sequences were evaluated on 15 nm thick Si 0.6 Ge 0.4 layers with different Queue-times (15 min and 8 hours) between wet and Siconi® treatments. Without any air break, the Siconi® process was followed by a low temperature H 2 bake (at 20 Torr and a temperature less than 700°C) and a re-epitaxy at 600°C of 15 to 17 nm of Si 0.6 Ge 0.4 . Secondary Ions Mass Spectrometry ( Figure 1 ) showed that a “chemical oxide - Siconi” sequence yielded a definite reduction of the interfacial oxygen concentration. Even with 8 hours of Q-time, concentrations were very low with these sequences. They were (i) more than one order of magnitude lower than with a regular “HF-HCl” (i.e. a “HF-Last”) wet cleaning and (ii) several times lower than with Siconi® only. Atomic Force Microscopy (AFM) images of the surfaces ( Figure 2 ) of ~ 30 nm thick Si 0.6 Ge 0.4 layers (after epitaxial regrowth) showed the presence of numerous islands after the use of “chemical oxide - Siconi®” surface preparations. Those defects were associated with poor crystalline quality layers. This was surprising. Indeed, such sequences yielded a superior oxide removal efficiency (Fig. 1) and smooth and defects-free SiGe surfaces just after their use (i.e. without any re-growth). Other epitaxial regrowth schemes using solely “HF/HCl” or Siconi® treatments did not result in such defects. The use of “chemical oxide - Siconi®” sequences must have resulted, after oxide removal, in SiGe surfaces richer in germanium than the “bulk” concentration (40%). They were then more sensitive to 2D-3D transitions during the H 2 bake than “regular” SiGe 40% surfaces. Ge-rich islands were thus formed during the H 2 bake that followed the “chemical oxide-Siconi®” sequence, destabilizing the epitaxial re-growth. In order to prevent surface islanding after "chemical oxide-Siconi®" sequences, we have then evaluated the interest of adding dichlorosilane (DCS) to H 2 during the temperature stabilization (just after loading inside the epitaxy chamber), the temperature ramping-up then the H 2 bake itself. Our aim was to encapsulate the extreme surface with a few atomic planes of Si in order to prevent 3D transitions. The reason why DCS was used was the following: with this chlorinated precursor, the homo-epitaxial Si growth rate decreased exponentially with the temperature (E a > 2eV, typically), with a lower “boundary” of 650°C, at which it was only 5 Å/min. When sent on a SiGe surface at T < 650°C, growth with DCS essentially stopped as soon as a switch over to a pure Si surface occurred, resulting in really thin Si caps. The H 2 annealing prior to SiGe epitaxy was divided into three steps: 1) low temperature stabilization of the wafer (after loading) ; 2) ramping-up to the bake temperature ; 3) low thermal budget H 2 bake (2 min. at T < 700°C). Three epitaxial regrowth schemes, with "HF/HCl-SC1-Siconi®" surface preparations then injections of dichlorosilane during step 1) only, steps 1) and 2) or steps 1), 2) and 3), were evaluated. As shown by AFM ( Figure 3 ), injection of DCS during the various annealing phases drastically reduced the density of 3D defects or suppressed them. The Si spacer thickness between the 15 nm thick Si 0.6 Ge 0.4 layer and the 17 nm of re-epitaxy after the addition of DCS during steps 1) and 2) was 2 nm only ( Figure 4 ). This is acceptable from an integration point of view, especially in SiGe:B sources and drains grown on top of high hole mobility SiGe channels, as such stacks will be germano-salicided afterwards, anyway. Figure 1

Strained Silicon On Insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, this new technology potentially combines enhanced devices scalability allowed by thin films and enhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate by experimental results how a layer transfer technique such as the Smart Cut™ technology can be used to obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments and characterizations will be used to characterize these engineered substrates and show that they are compatible with the applications.

• The high reactivity of GeSn surfaces to air-reoxidation limits the performances of ex-situ treatments before metallization . • Sn depletion with the HF- based wet treatment • HF and plasma (Argon and Helium) treatment reduce the native oxide amount without morphological impact.

Before metal deposit or epitaxial regrowth steps, efficient surface preparations are mandatory in order to remove both contaminants (C, F) and surface oxides. In this paper, we assess several cleaning sequences and compare their efficiency toward GaAs oxides removal. As III/V materials are very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi chamber) might be useful on GaAs surfaces. This way, the queue-time issues associated with wet surface preparations could be avoided. In this study, GaAs substrates were chemically oxidized to first characterize the oxide removal efficiency of HF, HCl and Siconi processes. Then, a new surface preparation strategy was proposed based on i) a wet chemical treatment followed by ii) a standard Siconi process. In situ Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxides and evaluate the impact of the various treatments on the GaAs surface. SIMS analyses were used to measure/quantify the efficiency of surface preparations on Carbon and Arsenic / Gallium oxides removal. (C) 2019 The Electrochemical Society.

A post-etch residue cleaning formulation, based on balancing the aggressiveness of hydrofluoric acid with its well-known residue removal properties is introduced. In a series of investigations originally motivated by the cleaning challenge provided by high-k dielectric-based residues, a formulation platform is developed that successfully cleans residues resulting from the plasma patterning of tantalum oxide and similar materials while maintaining metal and dielectric compatibility. It is further shown that the fundamental advantages of this solution can be extended to the cleaning of other, more traditional post-etch residues, with no sacrifice in compatibility, as demonstrated by measurements on blanket films and through SEM data.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. TTOP=500 ° C) in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

This paper investigates the possibility to fine tune a fluorinated solution to dissolve Ta, Zr, or Hf containing residues left after plasma etch, with maximum selectively towards silicon dioxide without corroding Aluminum. In this work amorphous "as dep" HfO2 has been assumed and proven to be a valuable test vehicle to evaluate the chemistry ability to dissolve such residues selectively towards other materials. In solvent/water mixtures, HF doesn't significantly hydrate until water content is predominant in the mixture. Plus, High proton concentration is key to reach a good aluminum protection and significant HfO2 dissolution rate in aqueous fluorinated solutions. By combining these properties an industrial solution has been engineered that achieves good dissolution of Ta, Zr, or Hf based polymers without corroding aluminum.

The low temperature integration of new materials (such as SiGe channels for the holes) is mandatory in advanced metal oxide semiconductor field effect transistors (i.e. in 14nm technology node devices and beyond). In this paper, we have investigated the removal of SiGe oxides prior to Selective epitaxial Growth of Si or SiGe:B in Sources/Drains regions. A very efficient removal of contaminants (C, F, O…) is mandatory if the H2 bake that precedes epitaxy is removed because of thermal budget constraints. As germanium is very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi® chamber) might be useful on SiGe surfaces. This way, the queue-time issues associated with “HF-Last” (HF/HCl follow by deionization water rinse) processes in single wafer wet cleaning tools are avoided. Germanium-rich SiGe layers (Si0.6Ge0.4) were used to characterize the native oxide removal efficiency of “HF-Last” and Siconi® processes. Then, a new surface preparation strategy was developed based on i) a wet chemical oxide formation followed by ii) a standard Siconi® process whose efficiency towards SiO2 has conclusively been demonstrated. Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxide and evaluate the efficiency of that treatment on carbon, germanium oxide and silicon oxide.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<;100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<;400°C) have potential for low-power applications and allow for the stacking of multiple layers.

The different regimes encountered when submitting ultra-thin SOI structures implanted with arsenic to single pulse laser annealing with increasing energy density, are identified. It is found that nanosecond UV laser annealing can be successfully applied to rebuild a perfect monocrystalline SOI layer and reach arsenic activation levels at least as high as rapid thermal processing, with a reasonably large process window. Thanks to electrical and morphological characterizations, the defective or polycrystalline silicon obtained below the optimum range is evidenced, as well as the loss of monocrystalline nature of the silicon at the upper end of the process window.

We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. "STRASS" and "BOX creep" techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: the electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles.