In this paper, a robust and energy efficient pulse generator (PG), dedicated to pulse-triggered flip-flops (pulsed-FFs) in ultra-wide voltage range (UWVR) applications, is proposed. Pulsed-FFs are promising candidate for high-speed and low-power applications, thanks to their small data-to-output delay and their shareable PG. However, UWVR circuits work most of the time under the threshold voltage, where local variations lead to a huge spread in logic delays. Therefore, the designers have to ensure that the minimum width of the pulse signal activating the pulsed-FF is large enough to guarantee the correct functionality of the FF. On the other hand, a too large pulse window would lead to an increase of the hold time, and thus energy overhead for inserting delay buffers, which is not acceptable in energy-efficient circuits. This work presents a pulse generator exhibiting excellent performances in the three figures of merit of PGs. Postlayout simulations showed that, for a small area penalty, the robustness of the pulsed-FF is greatly improved.

Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.

The pre-silicon 22/20nm LSTP models we generated are available on-line and can be used for fair bulk vs. FD SOI benchmarks. The proposed modeling methodology unified for bulk and FD SOI can further be used to generate models for LOP process flavor and/or 16nm CMOS node.