Early investigations on vanadium in the cubic 3C-SiC polytype concluded that the luminescence of the center is not possible because the excited state is degenerate with the conduction band. However, later work refuted this notion, demonstrating a doublet in photoluminescence (PL) at <^>1493-1495 nm, apparently associated with vanadium (V). In this work, we undertake a detailed experimental and theoretical study of the V center in 3C-SiC. We show that the vanadium PL can be seen as a recombination of an exciton bound to V, in contrast to the other two common hexagonal polytypes (4H-and 6H-SiC), where the PL is due to an interatomic transition of the 3d electron within the V center, according to a well-established model. We also show that the splitting observed in the PL lines is likely not inherent to the center and is due to stress present in the samples. Ideally, in a strain-free 3C-SiC material, the vanadium PL will comprise a single line, which makes the V center in this polytype attractive for applications as a qubit at moderate temperatures. This contrasts with the hexagonal polytypes where the splitting of the zero-phonon line is inherent to the center due to the crystal structure, which has a negative effect on the spin coherence at liquid helium temperature, and millikelvin temperatures are needed to improve the spin coherence.

Transistors capable of operating at cryogenic temperatures are key components for the fast and energy-efficient control and readout of qubits. However, the ultra-low power requirements and performance metrics are not met by conventional complementary metal oxide semiconductor technology, which has been optimized for room-temperature operation. Here, we propose to enhance Si-based Schottky junction field-effect transistors with ultra-thin layers of SiGeSn to address these issues. By combining single-elementary Al contacts to avoid dopant freezeout and utilizing a multi-gate transistor architecture, which suppresses reverse junction leakage, a fivefold increase in oncurrent and a threefold increase in peak transconductance were achieved compared to a Si reference device. Measurements down to 5K revealed a drain current modulation over nine orders of magnitude with improved inverse subthreshold slopes of 20mV/dec below 50K and 50% reduced threshold voltages, while the on-currents remain mostly temperature-independent, making the system interesting for cryogenic computing.

We present the design and implementation of a quantum-enabled readout Distributed Acoustic Sensor (Q-DAS), specifically developed for high-performance, long-range dynamic strain measurement. The Q-DAS utilizes a highly coherent laser source and a Superconducting Nanowire Single-Photon Detector (SNSPD) to accurately measure strain by analyzing the Rayleigh backscattered light along an optical fiber with a coherent OTDR topology. While prior research utilizing single-photon detection in distributed fiber optic sensing has primarily focused on temperature sensing, this work represents a significant advancement by applying this quantum-enabled-readout optical detection for dynamic strain measurement. Preliminary results demonstrate exceptional performance, achieving distributed strain measurement over a link-loss equivalent of 112.5 km of optical fiber while accurately reconstructing low-frequency (∼ few Hz) vibration signals. By suppressing receiver/electronics-noise limitations and operating in a photon-statistics-dominated (shot-noise-dominated) detection regime, this architecture establishes a foundation for robust, extra long-range physical sensor networks suitable for critical applications such as seismic and submarine cable monitoring.

Today, advancements in the study of complex interacting quantum systems and in unlocking their technological potential towards widespread application rely on the efficient, scalable realization of essential quantum hardware components on well-established material platforms. In this context, silicon (Si) color centers (CCs) [1] have recently emerged as a new promising system class for single-photon sources [2], light–matter interfaces [3] and quantum memories [4]. The high expectations arise from the rich electronic, optical, and spin properties of these predominantly carbon-impurity-based optically-active defects, their zero-phonon emission at telecom wavelengths, the suppression of decoherence mechanisms if integrated with isotopically purified 28 Si, as well as the compatibility with mature Si photonics and respective processing techniques. However, despite the wide availability of the required framework technology, fully exploiting the capabilities of Si CCs still requires a deeper understanding of their fundamental physical properties at a single defect level as well as the development of reliable, deterministic fabrication and tuning methods. One key challenge persists in the stochastic nature of ion-implantation commonly used for their creation [1-3], which lacks precise control over the resulting vertical emitter position. This restricts the effectiveness of matrix-engineering strategies and leads to low yield and poor reproducibility in applications that demand nanoscale spatial accuracy for optimal photonic coupling [5] and device integration. A recently introduced alternative approach addresses this issue by employing an entirely different, fully epitaxial method for the fabrication of Si CCs based on ultra-low-temperature (ULT) molecular beam epitaxy (MBE) [6]. In general, ULT-MBE [7,8] has already proven to be a highly versatile technique for the development of novel classical group-IV-semiconductor-based electronic [9,10] and optoelectronic [11] devices and holds significant potential for quantum science and technology. This contribution presents the ULT growth of carbon-doped Si:C layers at temperatures ≤ 310 °C, which enables the self-assembly of Si CCs confined to a specific epilayer and thus allows control over their vertical position within a structure with sub-nanometer precision. The predominantly observed G′ center [6,12] - identified as a previously unknown derivative of the well-known G center [1,2] - exhibits bright zero-phonon emission at ~1300 nm within the telecom O-band. An exceptionally pristine growth environment, combined with the higher thermal stability of the G′ center, permits subsequent float-zone-grade Si overgrowth, yielding emitters of high optical quality and enabling direct integration into p(-i)-n light-emitting diodes [12] for electrical pumping or tuning. The crucial role of the present growth conditions on the spectral properties of the formed Si CCs and unintended impurity incorporation is highlighted within growth-pressure-dependent studies. Finally, a systematic optimization of the active Si:C layer growth temperature combined with post-growth rapid thermal annealing for further fine-tuning of the Si CC lateral density will be presented, enabling the successful isolation of single G’ emitters in micro-photoluminescence and single-photon correlation measurements. References [1] M. Khoury and M. Abbarchi, J. Appl. Phys. 131 , 200901 (2022) [2] W. Redjem, et al ., Nat. Electron. 3 , 738 (2020) [3] M. Dobinson, et al ., Nat. Photon. 19 , 1132 (2025) [4] P. Udvarhelyi, et al ., npj Comput. Mater. 8, 262 (2022) [5] T. Poempool, et al. , Opt. Express 31 , 15564 (2023) [6] J. Aberl, et al. , Adv. Mater. 36 , 2408424 (2024) [7] A. Salomon, et al. , Phys. Status Solidi A 219 , 2200154 (2022) [8] C. Wilflingseder, et al. , ACS Appl. Electron. Mater. 6 , 9029 (2024) [9] A. Fuchsberger et al ., IEEE J-EDS 12 , 83 (2024) [10] A. Fuchsberger et al ., IEEE Electron Device Lett. 46 , 1429 (2025) [11] A. Salomon, et al ., arXiV: 2409.11081 (2024) [12] A. Salomon, et al ., ACS Photonics 12 , 2364 (2025)

Artificial atoms based on color centers in silicon (SiCCs) have recently emerged as promising candidates for highly integrable and scalable key components in photonic quantum technology, including telecom single-photon sources and spin memory devices. A novel all-epitaxial fabrication technique for SiCCs, based on ultra-low-temperature (ULT) molecular beam epitaxy (MBE), addresses limitations of conventional fabrication via ion implantation, such as vertical ion straggle and collateral crystal lattice damage. This method solely relies on self-assembly of SiCCs during kinetically-limited growth of (carbon-doped) Si(:C) at ULTs < 350°C. The latter requires an extraordinary pristine growth environment to prevent unintended defect formation caused by the incorporation of impurities from the background vapor; however, so far, no study has specifically addressed how exactly the vacuum conditions during epitaxy influence SiCC formation, their optical properties, and the quality of the surrounding crystal matrix. Here, we investigate the impact of the growth pressure and the substrate temperature on the self-assembly and photoluminescence (PL) properties of important SiCCs, such as W, G, G', and T centers. Further, we use PL and Doppler broadening variable energy positron annihilation spectroscopy to emphasize the role of the growth pressure in suppressing the luminescence background, which is crucial for advancing quantum photonics applications.

Reconfigurable field-effect transistors (RFETs), allowing dynamic run-time switching between n- and p-type operation, are already considered a viable CMOS add-on technology to enable adaptive computing concepts. Beyond that, exploiting the multi-gate architecture of RFETs can also be beneficial for analog circuits but has been less explored. Here, we experimentally demonstrate an adaptive current mirror based on Ge RFETs with the ability of electrostatic compensation of device-to-device variations, enabling an ideal current mirror that can even be switched between n- and p-type operation. Furthermore, the IOUT/IIN-ratio can be adjusted electrostatically without the need for additional devices. This enhances the abilities of traditional current mirrors that are not adjustable after manufacturing without the need for complex additional circuitry.

Silicon color centers (SiCCs) have recently emerged as potential building blocks for light emitters in Si photonics, quantum emitters with spin storage capabilities, and Si-based quantum repeaters. We have recently developed a noninvasive method to engineer carbon-related SiCCs confined to ultrathin nanolayers within a pristine crystalline environment, which is of utmost importance for the photostability of SiCCs. Here, we demonstrate embedding these C-doping-based SiCCs into the only 9 nm wide intrinsic region of a p-i-n diode using the epitaxial self-assembly of color centers. We report electrically pumped light emission with an exponential increase in the intensity as a function of the driving current until saturation. We associate this property with the shift of quasi-Fermi-level position upon electrical driving, which simultaneously improves the spectral homogeneity of the engineered SiCCs. Despite the low employed growth temperatures, our study demonstrates the electrical control and driving of near-infrared emitters in high-quality silicon diodes, an essential milestone for advancing classical and quantum optoelectronics.

Modulation acceptor doping allows for the generation of holes as free charge carriers in the semiconductor by introducing acceptor states in the gate oxide. This overcomes the limitations of nanoscale doping and maintains the characteristics of impurity-free semiconductor channels. Here, we demonstrate modulation doping via Al-induced acceptor states in a SiO2 gate-dielectric of a SiGe-based Schottky barrier field-effect transistor. Compared to an undoped reference sample, pulsed and temperature-dependent electrical measurements revealed a 4170-times higher conductivity of the ungated SiGe channel and a 3-fold increase in the p-type on-state current when the device is operated as a transistor. Importantly, the application of modulation doping to Ge-rich SBFETs may contribute to nanoscale devices with lower supply voltages and faster switching speeds.

Exploiting the capabilities of multi-gated transistors is a promising strategy for adaptive and compensative analog circuits. Typically, reconfigurable transistors, which can be switched between n-and p-type operation at runtime, are used as universal transistors in fine grain programmable digital circuits. However, in the analog domain, by operating the transistors deliberately in intermediate states, they enable adjustments to application-specific requirements and allow for compensation of undesired deviations. Here, we propose a Ge-on-SOI transistor circuit primitive that enables an adaptable circuit design featuring n-and p-type common source (CS) and drain circuits, with electrostatically tuneable output-to-input ratio. Most notably, combined experimental and simulation studies promote verification and scalability assessment. Finally, the first experimental evidence of the electrostatic compensation of transistor/circuitpath-related device-to-device inequalities is shown in a differential amplifier featuring adaptable gain.

Integrating Ge onto SOI should enhance the drive currents and switching speeds of transistors. However, Ge on insulator platforms have fallen short of providing these benefits and are additionally facing processing issues and high fabrication costs. To cope with these issues, we use an ultra-low-temperature molecular-beam epitaxy growth of Ge layers on SOI and strained SOI substrates, as device prototyping platforms. Thereof, we obtain symmetric IV-on-states in Ge based reconfigurable transistors, enabling to investigate the temperature-dependent gating capabilities and identify the dominant transport mechanisms. In this respect, to give a comprehensive picture of the influence of different parameters on transport mechanisms, temperature-dependent gate- and biasdependent current-voltage data was evaluated constructing 2-D colormap representations.

We study the monolithic quasi-ohmic contact formation with single-elementary Alto Ge1-xSnx channel devices with various Sn concentrations between 0.5 % and 4 %. Thereby we investigate the influence of increasing Sn content on the electrical transport properties in field-effect transistors fora wide temperature range between 77 K and 400 K. At low temperatures, the devices exhibit improved performance metrics, promising for cryoCMOS applications. Compared to pure Ge control devices, the introduction of Sn into the channel leads to a 20 times increased on-current. Ina multi-gate architecture, we analyze the decoupled influence of the carrier injection through the metal-semiconductor junction and the channel conduction.

The discovery of quantum emitters (QEs) in two-dimensional (2D) materials has triggered a surge of research to assess their suitability for quantum photonics. Although position-controlled QEs are routinely fabricated using static strain gradients, the use of dynamic strain fields to control the brightness of QEs has not been explored yet. Here, we address this challenge by introducing a novel device in which WSe2 monolayers are integrated onto piezoelectric pillars that provide both static and dynamic strains. The static strains are first used to induce the formation of QEs, while their energy and brightness are then controlled via voltages on piezoelectric pillars. Numerical simulations show that these effects are due to a strain-induced modification of the confining-potential landscape, which leads to a net redistribution of excitons among the different QEs. Our work provides a method to dynamically control the energy and brightness of QEs in 2D materials.

Advancing SOI-based transistors with Ge-rich layers aims to increase device performance in terms of on-state operation and switching speed. Here, we investigate multi-heterojunction SiGe-based Schottky barrier FETs with Ge concentrations up to 75% by means of temperature- dependent electrical characterizations to identify the transport regimes and the effective barrier heights with a thermionic-emission-based model. Importantly, incorporating 33% Ge gives the best compromise for n- and p-type on-state symmetry. As the Ge concentration increases, the p-type on-state current becomes dominant, which is interesting for low-power p-type transistors.

Implementing only tens of nanometer-thin Ge and Ge-rich SiGe nanosheets on SOI is expected to boost performance metrics of next-generation electronic devices, such as reconfigurable field effect transistors [1]. However, an inherent lattice mismatch between Ge and Si drastically limits the thickness of high-quality Ge layers on Si to a few monolayers, i.e., far too thin for practical nanosheet device applications. Thus, to date, many prototype Ge-rich nanoelectronics device concepts are based on nanowires' vapor-liquid-solid (VLS) growth. Since these nanowires grow on untypical (111) substrates and in a vertical manner, they need to be picked and placed onto Si(001) substrates: A serial process and, thus, barely scalable. Therefore, whenever two-dimensional nanosheets of a material are available, they provide distinct advantages with respect to the scalability of the device integration. Here, we show that pure Ge and SiGe alloyed nanowires can be formed top-down from nanosheets. We show that devices from nanowires based on Ge on SOI nanosheets have excellent quality and can outperform other material platforms, such as VLS nanowires or devices based on GeOI substrates, thereby enabling extended device functionalities [2]. For high Ge contents and typical Ge growth temperature above 500°C, the achievable thickness of pseudomorphic, defect-free (Si)Ge epilayers is just a couple of monolayers if grown directly on Si(001) substrates [3,4]. Above this thickness, the inherent strain between the layer and SOI substrate leads to harmful plastic or elastic relaxation under common growth conditions. We depart from established (Si)Ge epitaxy temperatures of ≥500°C and employ molecular beam epitaxy (MBE) growth at ultra-low temperatures (ULT), ranging from 100°C to 350°C [5,6]. We show that the lowered surface kinetics leads to a pronounced layer supersaturation, allowing us to access layer thicknesses about an order of magnitude larger than previously reported values. Also, in contrast with previous results for ULT epitaxy [7], we do not observe layer amorphization even for growth at 100°C. Here, we highlight that pristine growth pressures deep in the ultra-high vacuum range (≤10-10 mbar) are crucial to keep the density of unwanted impurities in the (Si)Ge layers to a minimum and, thus, enable excellent electrical and optical properties of the grown heterostructures. These low growth pressures are particularly important in ULT growth since the low thermal budget impedes the efficient desorption of residual gas molecules from the substrate. We further show the fabrication of nanosheet transistors based on fully strained, defect-free (Si)Ge epilayers grown directly on SOI substrates [2,8,9]. For these devices, properties like thickness, SiGe(Sn) content, barrier material, and doping can be conveniently tuned during the epitaxy process beyond past limitations. We demonstrate that these nanosheets are a highly scalable platform for emerging devices, such as reconfigurable transistors with excellent performance [2,8,9] and highly symmetric n- and p-type transistor characteristics. Notably, the ULT-grown nanolayers withstand high-temperature device fabrication steps such as SiO2 formation and Al-SiGe exchange [2,8,9]. References [1] A. Heinzig et al., Nano Lett. 12, 119 (2012). [2] A Fuchsberger et al., IEEE Journal of the Electron Devices Society 12, 83 (2024) [3] H. Sunamura et al., Appl. Phys. Lett. 66, 3024 (1995). [4] M. Brehm et al., Nanotechnology 28 (39), 392001 (2017). [5] A. Salomon et al., physica status solidi (a) 219, 2200154 (2022). [6] J. Aberl et al., https://arxiv.org/abs/2402.19227v1 [7] D. J. Eaglesham; M. Cerullo, Appl. Phys. Lett. 58, 2276 (1991). [8] L. Wind et al., Small 18 (44), 2204178 (2022). [9] A. Fuchsberger, et al., Advanced Electronic Materials, 2201259 (2023).

We investigate the nanoheteroepitaxy (NHE) of SiGe and Ge quantum dots (QDs) grown on nanotips (NTs) substrates realized in Si(001) wafers. Due to the lattice strain compliance, enabled by the nanometric size of the tip and the limited dot/substrate interface area, which helps to reduce dot/substrate interdiffusion, the strain and SiGe composition in the QDs could be decoupled. This demonstrates a key advantage of the NHE over the Stranski-Krastanow growth mechanism. Nearly semi-spherical, defect-free, similar to 100 nm wide SiGe QDs with different Ge contents were successfully grown on the NTs with high selectivity and size uniformity. On the dots, thin dielectric capping layers were deposited, improving the optical properties by the passivation of surface states. Intense photoluminescence was measured from all samples investigated with emission energy, intensity, and spectral linewidth dependent on the SiGe composition of the QDs and the different capping layers. Radiative recombination occurs in the QDs, and its energy matches the results of band-structure calculations that consider strain compliance between the QD and the tip. The NTs arrangement and the selective growth of QDs allow to studying the PL emission from only 3-4 QDs, demonstrating a bright emission and the possibility of selective addressing. These findings will support the design of optoelectronic devices based on CMOS-compatible emitters.

Germanium has already successfully entered Si technology through electronics and photonics applications [1,2]. However, due to the inherent lattice mismatch between Ge and Si, high-crystalline SiGe epitaxial layers of a sufficient thickness could only be grown for relatively low Ge concentration (<40%). At higher concentrations, the epitaxial SiGe layers relax the strain through either plastic or elastic relaxation. Thus, for about 2% (and 4%) strain between substrate and epilayer, only layer thicknesses of < 2nm (<0.5 nm) can be grown before elastic relaxation leads to quantum dot formation. In principle, such epitaxial Ge-rich QDs on Si(001) substrates can be successfully used to enhance the light emission properties of SiGe material [3-7]. However, planar Ge-rich two-dimensional layers would be preferred for efficient large-scale integration and reliable addressing of the nanostructures. Here, we demonstrate that ultra-low temperature (ULT) growth, carried out in a temperature window between 100°C and 350°C, is the key to extensive epilayer supersaturation, leading to layer thicknesses that are about one order of magnitude larger than what can be achieved by conventional epitaxy [8]. Thereby, we highlight that molecular beam epitaxy is the suitable choice for ULT growth since, using chemical vapor deposition methods for Si deposition, the ULT range cannot be reached due to the lack of precursor decomposition. However, we also stress that the chamber conditions during the growth need to be excellent in order to limit detrimental point defect formation during epitaxy. If these preconditions are met, ULT growth can lead to up to now unattainable layer structures. These, in turn, can be used, e.g., for the first available double heterostructure (DHS) light-emitting diodes in the group-IV system. We demonstrate that these LEDs, emitting in the telecom band, work efficiently up to room temperature and above. Light emission above room temperature is eventually limited by minority carrier injection. Additionally, novel electronic device concepts such as reconfigurable field effect transistors (RFETs) can be realized using several nanometer-thick Ge layers grown directly on silicon on insulator substrates. We argue that these devices have distinct advantages in performance and integration possibilities as compared to conventional nanoelectronics devices based on Ge-rich material, for which typically vertically grown nanowires are employed [9,10]. References [1] I. A. Fischer, et al., APL Photonics 7 , 050901 (2022). [2] J. Aberl, Opt. Express 27 , 32009– 32018 (2019). [3] M. Grydlik et al., ACS Photonics 3 , 298–303 (2016). [4] M. Grydlik et al., Nano Lett. 16 , 6802–6807 (2016). [5] M. Brehm et al., Nanotechnology 28 , 392001 (2017). [6] P. Rauter et al., ACS Photonics 5 , 431-438 (2018). [7] F. Murphy-Armando et al., Phys. Rev. B 103 , 085310 (2021). [8] A. Salomon et al., Phys. Status Solidi A 219 (17), 2200154 (2022). [9] L. Wind et al., Small 18 (44), 2204178 (2022) [10] A Fuchsberger et al., Advanced Electronic Materials, 2201259 (2023)

A promising approach to advance electronics beyond static operations is to enhance state-ofthe- art systems by the functional diversification of transistors. Here, we experimentally demonstrate that an ultra-thin Ge channel implemented on a Si on insulator platform enables run-time switchable symmetric pand n-type field-effect transistor operability as well as the prominent feature of distinct room-temperature negative differential resistance. Temperature dependent bias spectroscopy is utilized to map electronic transport in these so called negative differential resistance mode reconfigurable transistors. Thereof, a profound understanding of the involved transport physics and electrostatic gating mechanisms is obtained and evaluated. Further, we show that a multi-gate negative differential resistance reconfigurable transistor can effectively replace a cascode of negative differential resistance devices, contributing to a smaller area footprint, and reduced latency of critical paths. Notably, the experimentally obtained multi-heterojunction transistors constitute the first chip-scale platform that combines efficient polarity control as well as sizeand energy-efficient room-temperature negative differential resistance, providing an inherent component of emerging neuromorphic computing.

We report on electroluminescence spectroscopy experiments demonstrating room-temperature light emission from heavily alloyed SiGe quantum dots, for which the light emission properties are enhanced by incorporated split-[110] self-interstitials. The quantum dots are formed during molecular beam epitaxy deposition of Si0.6Ge0.4 alloys on n-doped silicon-on-insulator substrates. To create the split-[110] self-interstitials the quantum dots were co-implantated in-situ using Si and Ge ions. The hybrid emitters were further embedded into the intrinsic region of a p-i-n diode structure to enable electrical pumping. Similar to previous theoretical results on unstrained Ge-based quantum dots containing these defects, radiative direct transitions are possible for these SiGe light emitters. However, in SiGe dots these transitions are not at the Brillouin zone center. Instead, first-principles calculations indicate that the presence of the split-[110] self-interstitial defect in strained and unstrained SiGe can lead to optically direct transitions in momentum space in the X-direction of the Brillouin zone.

Silicon-based color-centers (SiCCs) have recently emerged as quantum-light sources that can be combined with telecom-range Si Photonics platforms. Unfortunately, using current SiCC fabrication, deterministic control over the vertical emitter position is impossible due to ion-implantation's stochastic nature. To overcome this bottleneck towards high-yield integration, we demonstrate a radically innovative creation method for various SiCCs, solely relying on epitaxial growth of Si and C-doped Si at atypically-low temperatures in a ultra-clean growth environment. These telecom emitters can be confined within sub-1nm thick layers embedded at arbitrary vertical positions within a highly crystalline Si matrix. Tuning growth conditions and doping, different SiCC types, e.g., W-centers, T-centers, G-centers, or derivatives like G'-centers can be created, which are particularly promising as Si-based single-photon sources and spin-photon interfaces. The zero-phonon emission from G'-centers can be conveniently tuned by the C-concentration, leading to a systematic wavelength shift and linewidth narrowing towards low emitter densities.