Real-time support for an iris recognition algorithm is a considerable challenge for a portable system that is commonly used in the field. In this paper, an efficient parallel and pipeline architecture design for the feature extraction and template matching processes in the Ridge Energy Direction (RED) algorithm for iris recognition is presented. Several techniques used in the proposed architecture design to reduce the computational complexity while supporting a high performance capability include (i) a circle approximation method for the iris unwrapping process, (ii) a parallel design with an on-chip buffer for 2D convolution in the feature extraction process, and (iii) an approximation method for log(2) and inverse-log(2) conversion in the template matching process. Performance analysis shows that the proposed architecture achieves a speedup of 881 times compared to the conventional method. The proposed design can be integrated with an embedded microprocessor to realize a complete system-on-chip solution for a portable iris recognition system.

Face detection is the determination of the positions and sizes of faces, primarily human, within digital images and videos, often as a component of a broader facial recognition system. It is seen as technologically mature, yet its operational performance typically remains sub-optimal, even within the less difficult frontal face detection tests. Empirical evidence shows that the Viola–Jones framework, a standard face detection solution with generally superior performance and other desirable properties, underdetects in some instances. Some true faces survive all but the final stages of the rejection cascade, resulting in missed faces. A hybrid framework consisting of a neural network following a truncated Viola–Jones cascade is constructed in an attempt to recover the undetected faces. Presumably, the neural network could fine tune and augment the face decision. Its inputs are a subset of the thresholding (detection) values of a rejection cascade's intermediate stages. Experiments reveal significantly improved performance, with increased detection rates if no false alarm increases are tolerated, with a greater detection rate increase if some false alarm increases are acceptable, and with a substantial false alarm reduction with no detection reduction. These improved face detection results could address shortcomings in widely-varying applications.

For digital imagery, face detection and identification are functions of great importance in wide-ranging applications, including full facial recognition systems. The development and evaluation of unique and existing face detection and face identification applications require a significant amount of data. Increased availability of such data volumes could benefit the formulation and advancement of many biometric algorithms. Here, the utility of using synthetically generated face data to evaluate facial biometry methodologies to a precision that would be unrealistic for a parametrically uncontrolled dataset, is demonstrated. Particular attention is given to similarity metrics, symmetry within and between recognition algorithms, discriminatory power and optimality of pan and/or tilt in reference images or libraries, susceptibilities to variations, identification confidence, meaningful identification mislabelings, sensitivity, specificity, and threshold values. The face identification results, in particular, could be generalized to address shortcomings in various applications and help to inform the design of future strategies. (C) 2016 SPIE and IS&T

For the past 40 years, Moore's law has predicted the rapid growth of the computer industry. In the past few years, however, this growth has slowed for central processing units (CPUs). Instead, there has been a shift to multicore computing, specifically with the general purpose graphic processing units (GPUs). Conventional CPUs have between two and eight cores, but the GPUs can have hundreds, even thousands of cores. By parallelizing code, the computing power of these cores can be utilized to greatly accelerate the performance of certain algorithms. The GPUs, however, have been known to consume more power than the conventional processing units. While previous research has focused on the impact that the GPUs have on performance, there are much fewer studies on the impact of GPUs on energy consumption and efficiency. Some researchers have hypothesized that if the performance of an algorithm was sufficiently increased on a GPU, then the accelerated time would actually cause the GPU to consume less energy. For the first time to our knowledge, we study the energy efficiency of a GPU with an application to iris recognition. Using GPU-based code written in the C++ compatible compute unified device architecture language, energy consumption tests are performed on basic image processing techniques, including image inversion, thresholding, dilation, erosion, and memory/computationally intensive calculations, such as the template matching. We demonstrate that the portions of these algorithms implemented on the GPU reduce energy consumption by as much as 272 times.

An efficient parallel architecture design for the iris unwrapping process in a real-time iris recognition system using the Bresenham Circle Algorithm is presented in this paper. Based on the characteristics of the model parameters this algorithm was chosen over the widely used polar conversion technique as the iris unwrapping model. The architecture design is parallelized to increase the throughput of the system and is suitable for processing an inputted image size of 320 × 240 pixels in real-time using Field Programmable Gate Array (FPGA) technology. Quartus software is used to implement, verify, and analyze the design's performance using the VHSIC Hardware Description Language. The system's predicted processing time is faster than the modern iris unwrapping technique used today∗.

Human face detection in digital images and videos is a mature technology, yet its operational performance is generally sub-optimal. Any improvement would be beneficial in many applications. Some computer vision approaches to object recognition, including face detection, have begun to achieve impressive levels of accuracy and robustness, yet lack a clear connection to known cortical constructs. This motivates investigations of biologically-inspired techniques. The mechanisms by which contour shapes, and in particular faces, are represented in cortex and the means that neural models and computer vision algorithms can more closely approximate these are examined. The OpenCV library implements a standard face detection solution, the Viola-Jones detector. A hybrid framework, with a truncated Viola-Jones cascade followed by neural population models, is considered in this current work.

Improvements in face detection performance would benefit many applications. The OpenCV library implements a standard solution, the Viola-Jones detector, with a statistically boosted rejection cascade of binary classifiers. Empirical evidence has shown that Viola-Jones underdetects in some instances. This research shows that a truncated cascade augmented by a neural network could recover these undetected faces. A hybrid framework is constructed, with a truncated Viola-Jones cascade followed by an artificial neural network, used to refine the face decision. Optimally, a truncation stage that captured all faces and allowed the neural network to remove the false alarms is selected. A feedforward backpropagation network with one hidden layer is trained to discriminate faces based upon the thresholding (detection) values of intermediate stages of the full rejection cascade. A clustering algorithm is used as a precursor to the neural network, to group significant overlappings. Evaluated on the CMU/VASC Image Database, comparison with an unmodified OpenCV approach shows: (1) a 37% increase in detection rates if constrained by the requirement of no increase in false alarms, (2) a 48% increase in detection rates if some additional false alarms are tolerated, and (3) an 82% reduction in false alarms with no reduction in detection rates. These results demonstrate improved face detection and could address the need for such improvement in various applications.

In this paper, a resource efficient architecture design for the circular Hough transform based on Field Programmable Gate Array (FPGA) technology is presented. The circular Hough transform is implemented to detect iris boundary in a binary edge image. A novel modular design is proposed to reduce the required memory space by 93% compared to the direct implementation while maintaining a high detection rate over 92%. The parallel-pipelined implementation of the proposed architecture demonstrates a high speed processing capability that is suitable to support real-time iris recognition in resource constrained systems. Therefore, the proposed technology can be used in portable consumer devices such as mobile phones and tablets where iris recognition application is involved.

In this work, a hardware-software co-design is proposed to effectively utilize FPGA resources for a prototype of an automated video surveillance system on a programmable platform. Time-critical steps of a foreground object detection algorithm are designed and implemented in the FPGA's logic elements to maximize parallel processing. Other non time-critical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Custom and parallel processing modules are integrated into the video processing chain by a streaming protocol that aggressively utilizes on-chip memory to increase the throughput of the system. A data forwarding technique is incorporated with an on-chip buffering scheme to reduce computations and resources in the window-based operations. Other data control interfaces are achieved by software drivers that communicate with hardware controllers using Altera's Memory-Mapped protocol. The proposed prototype has demonstrated real-time processing capability that outperforms other implementations.

In this paper, a real time FPGA-based iris segmentation system is presented. The segmentation method implements the Canny edge detection algorithm and a circle search to detect an iris in an image or video frame. The proposed high performance architecture utilizes on-chip memory to significantly improve the throughput of the pipelined and parallel structure. A data forwarding technique is incorporated in the design to efficiently utilize the FPGA's embedded resources. The proposed architecture demonstrates a high speed processing capability that will facilitate the use of dedicated hardware to support an iris recognition application for large databases.

The iris is currently believed to be one of the most accurate biometrics for human identification. The majority of fielded iris identification systems use fractional Hamming distance to compare a new feature template to a stored database. Fractional Hamming distance is extremely fast, but mathematically weights all regions of the iris equally. Research has shown that different regions of the iris contain varying levels of discriminatory information when using circular boundary assumptions. This research evaluates four statistical metrics for accuracy improvements on low resolution and poor quality images. Each metric statistically weights iris regions in an attempt to use the iris information in a more intelligent manner. A similarity metric extracted from the output stage of an artificial neural net-work demonstrated the most promise. Experiments were performed using occluded, subsampled, and motion blurred images from the CASIA, University of Bath, and ICE 2005 databases. The neural network-based metric improved accuracy at nearly every operating point. (C) 2011 SPIE and IS&T. [DOI: 10.1117/1.3549886]

FPGA devices with embedded DSP and memory blocks, and high-speed interfaces are ideal for real-time video processing applications. In this work, a hardware-software co-design approach is proposed to effectively utilize FPGA features for a prototype of an automated video surveillance system. Time-critical steps of the video surveillance algorithm are designed and implemented in the FPGAs logic elements to maximize parallel processing. Other non timecritical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Pre-tested and verified video and interface functions from a standard video framework are utilized to significantly reduce development and verification time. Custom and parallel processing modules are integrated into the video processing chain by Altera's Avalon Streaming video protocol. Other data control interfaces are achieved by connecting hardware controllers to a Nios-II processor using Altera's Avalon Memory Mapped protocol.

In the past two years the processing power of video graphics cards has quadrupled and is approaching super computer levels. State-of-the-art graphical processing units (GPU) boast of theoretical computational performance in the range of 1.5 trillion floating point operations per second (1.5 Teraflops). This processing power is readily accessible to the scientific community at a relatively small cost. High level programming languages are now available that give access to the internal architecture of the graphics card allowing greater algorithm optimization. This research takes memory access expensive portions of an image-based iris identification algorithm and hosts it on a GPU using the C++ compatible CUDA language. The selected segmentation algorithm uses basic image processing techniques such as image inversion, value squaring, thresholding, dilation, erosion and memory/computationally intensive calculations such as the circular Hough transform. Portions of the iris segmentation algorithm were accelerated by a factor of 77 over the 2008 GPU results. Some parts of the algorithm ran at speeds that were over 1600 times faster than their CPU counterparts. Strengths and limitations of the GPU Single Instruction Multiple Data architecture are discussed. Memory access times, instruction execution times, programming details and code samples are presented as part of the research.

Modern advancements in configurable hardware, most notably Field-Programmable Gate Arrays (FPGAs), have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. On the other hand, PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high performance. In this research project, our aim is to study the differences in performance of a modern image processing algorithm on these two hardware platforms. In particular, Iris Recognition Systems have recently become an attractive identification method because of their extremely high accuracy. Iris matching, a repeatedly executed portion of a modern iris recognition algorithm, is parallelized on an FPGA system and a Cell processor. We demonstrate a 2.5 times speedup of the parallelized algorithm on the FPGA system when compared to a Cell processor-based version.

Skin detection is the process of finding skin-colored pixels and regions in an image or a video. This process is typically used as a preprocessing step to find regions that potentially have human faces and limbs in images. Several computer vision approach es have been developed for skin detection. A skin detector typically transforms a given pix el into an appropriate color space and then use a skin classifier to label the pixel whether it is a ski n or a non-skin pixel. A skin classifier defines a decision boundary of the skin color class in the colo r space based on a training database of skin-colored pixels.