This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288-460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.

A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 ps pp ISI and 0.2 ps rms RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UI pp at 100 MHz and an input sensitivity of 20 mV pp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 2 31 -1 PRBS at BER 10 -12 over a channel with >21 dB loss at Nyquist frequency.

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 ps rms RJ, 0.8 ps pp DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mV ppd input sensitivity and a 0.7-UI pp high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 ps rms RJ, and 2 ps pp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm 2 and consumes 214 mW.

A synthesis-based bandwidth enhancement technique for CMOS amplifiers/buffers is presented. It achieves bandwidth-enhancement ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93 for passive network with balanced capacitive loads. By employing a step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Time-domain behavior of the proposed technique is examined. Two prototype amplifier/buffer circuits are designed using lower order passive networks to save chip area and circuit complexity. The test chips are fabricated in a 0.18 μm CMOS process, and measurements verify the frequency- and time-domain analyses. The amplifier provides 18.5 dB gain and 28 GHz bandwidth, while consuming 52 mW power from a 1.8 V supply.

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

This paper presents the design and implementation of a novel multi-antenna receiver front-end, which is capable of accommodating various multi-antenna schemes including spatial multiplexing (SM), spatial diversity (SD), and beamforming (BF). The use of orthogonal code-modulation at the RF stage of multi-antenna signal paths enables linear combination of all mutually orthogonal code-modulated RF received signals. The combined signal is then fed to a single RF/baseband/ADC chain. In the digital domain, all antenna signals are fully recovered using matched filters. Primary advantages of this architecture include a significant reduction in area and power consumption. Moreover, the path-sharing of multiple RF signals mitigates the issues of LO routing/distribution and cross-talk between receive chains. System-level analyses of variable gain/dynamic range, bandwidth/area/power trade-off, and interferers are presented. Designed for the 5-GHz frequency and fabricated in 0.18 mum CMOS, the 76 mW 2.3 mm2 two-antenna receiver front-end prototype achieves a 10-2 symbol error rate (SER) at 64, 77, and 78 dBm of input power for SM, SD, and BF, respectively, while providing 21-85 dB gain, 6.2 dB NF, and 10.6 dBm IIP3.

This paper presents the design of a novel 5 GHz multi-antenna RF front-end, which is capable of performing spatial multiplexing, spatial diversity, and beamforming. The use of a unique code-modulation scheme at the RF stages of the signal paths enables linear combination of all mutually orthogonal code-modulated received signals. The combined signal is then fed to a single RF/baseband/ADC chain, resulting in a significant reduction of power consumption and area, as well as mitigating the issue of LO routing/distribution. In the digital domain, all antenna signals are fully recovered. Fabricated in 0.18 mum CMOS, the 76 mW 2.3 mm2 two-antenna receiver front-end achieves a 10-2 SER at -64, -77, and -78 dBm of input power for SM, SD, and BF, respectively, while providing 85 dB gain, 6.2 dB NF, and -10.6 dBm IIP3.

The design and implementation of a 2.5-3.2 GHz LC-VCO incorporating a varactor-less tuning technique is presented. The VCO's oscillation frequency is tuned differentially by varying the effective inductance of the oscillators. Fabricated in a 0.18 mum CMOS process, the prototype VCO achieves 24% continuous tuning range without varactors. The circuit draws 7-15 mA current from a 1.8 V power supply. The measured phase noise is varying between -102 dBc/Hz and -111 dBc/Hz at 1 MHz offset across the tuning range.

A conventional differential pair LC oscillator is capable of generating only a single fundamental oscillation frequency. This brief presents the theoretical study of a novel oscillator that incorporates higher order LC filters to produce multiple oscillation frequencies that may be several octaves apart. These multiple oscillation frequencies are obtained from a single oscillator, thereby reducing the area of the circuit when being used for multistandard wireless applications. Moreover, a multi-order oscillator does not suffer from large parasitic capacitances from switches, which is a common drawback in switched-inductor tuned oscillators. A detailed analysis is carried out, and useful design insights are provided.

A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.