A simple three-dimensional void growth model is presented that can be used to simulate the resistance behavior in narrow copper lines upon thermo-electrical stressing. The output of the model is compared with experimental results obtained from electromigration tests carried out on single damascene copper lines encapsulated by a physical vapor deposition tantalum nitride–tantalum barrier. The electromigration resistance profiles are found to depend on different line and barrier parameters. The simulations yield a better understanding of the physical phenomena responsible for changes in the resistance profiles. The effect of a void cutting a copper line is seen as an asymptotic increase or “jump” in the measured resistance profile. At that moment, the barrier shunts the current and the void does not necessarily induce a catastrophic failure. Therefore, more voids can be formed in the line upon electromigration (EM) stress; every void spanning the line initiates a “jump” in the resistance profile. The described model approximates the experimental results with sufficient accuracy. The model can be used to predict the height of the jumps, setting adequate failure criteria beforehand for the EM experiments. The simplicity and sufficient accuracy of this model allow for easy prediction and interpretation of the EM resistance traces.

Single damascene (SD) Cu/Aurorareg ULK interconnects with a minimum spacing of 50nm are achieved by using a metal hard mask (MHM) integration scheme, which enables to perform the resist ash before dielectric etch. This patterning scheme is used in combination with a low damage etch technique based on sidewall protection. Interconnect performance and reliability can be further improved by using Aurorareg ULK high modulus (HM), a low-k film with a reduced diffusivity as compared to Aurora ULK, and a comparable k-value of 2.7. The MHM approach results in a limited increase in integrated k-value by 0.1 for ULK HM vs. 0.3 for Aurorareg ULK. The median time dependent dielectric breakdown (TDDB) lifetime is well above the 10 years criterion for spacings down to the 50nm. Finally, the MHM integration scheme enabled fabrication of dual damascene interconnects with Aurorareg ULK HM

Dual damascene self-aligned air gap structures have been fabricated through selective removal of interline plasma-damaged SiOC material using dilute HF solutions after metal CMP. The extent of the gaps was shown to be tuneable. The creation of interline air gaps through removal of damaged dielectric yielded significant capacitance reduction plus in addition dielectric reliability improvement. The via-reliability of 2 metal-build air gap structures was tested by thermal cycling and constant thermal stress. No significant difference in via reliability was observed between SiOC interconnects with and without air gaps. However, failure analysis showed weak spots near the bottom of the barrier, which could be detrimental for dual damascene reliability. These weak spots at the barrier bottom could lead to catastrophic failures in both via and lines during electromigration stressing. Moreover, process-related issues such as bottom liner undercut and copper corrosion need to be controlled more stringent before this air gap approach can be successfully implemented.

Back-end-of-line (BEOL) reliability, comprising barrier, dielectric and current-carrying metal reliability, is a major challenge for future IC generations as the reliability margin of the dielectric/barrier/copper systems is shrinking. The impact of interconnect scaling on BEOL reliability is outlined and illustrated by low-k TDDB, electromigration and stress-induced-voiding results.

使用两种化学机械抛光剂得到的单层大马士革Cu导线表面起伏程度不同.扫描电镜观察到明显的缺陷出现在大起伏的Cu导线表面.这种表面缺陷导致早期失效比率剧增至几乎100%、电迁移寿命猛降至早期失效的量级、失效时间分布从多模变为单模,其相应的失效机制激活能为0.74±0.02 eV,这说明失效主要是由Cu原子沿导线表面扩散引起的.最弱链接近似被用来分析单根Cu导线:Cu导线被适当均分为若干相互串联、失效机制不同的Cu块,任何一个Cu块的失效都会使整根Cu导线失效.分析结果表明,虽然表面缺陷不是最快的失效机制,但大起伏Cu导线的表面缺陷密度是另一种的10 倍以上,这是其早期失效比率高和可靠性较低的主要原因.

Different CMP slurries are used to obtain single-damascene Cu wires with different surface fluctuations as well as 'intentional' surface defects in the lines with rougher surface. The presence of such intentional defects strongly increases the rate of early failures up to almost 100%, reduces electromigration lifetime rapidly to the level of early failures, and changes the multimodal failure distribution into a monomodal one. The activation energy (0.74 /spl plusmn/ 0.02 eV) for the failure mechanism associated With these intentional defects confirms a dominant surface diffusion. We show how a Weakest Link Approximation analysis can be applied to single lines by dividing the lines into relevant segments and assigning different failure mechanisms to the various segments. The WLA analysis confirms that, although surface defects are not the fastest early failure mechanism, the 10 times higher surface-defect density in the rougher lines is responsible for the observed high early-failure rate and poor reliability performance.

The electromigration behaviour of sub-100nm lines embedded in BD-I-1 low-k trenches has been studied. Very long lifetimes have consistently been observed. Moreover, lines do not fail abruptly but display a gradual resistance increase, which was shown to correspond to void growth along the length of the line. Furthermore, it has been shown that the number of line-spanning voids equals the number of inflection points in the resistance profile. Finally, the observed resistance profiles are also clearly related to the current strapping capacity of the incorporated 10/15 nm I-PVD TaN/Ta diffusion barrier.

Process conditions for preferential growth of the low-resistivity alpha-Ta phase in interconnect barriers using a second-generation I-PVD technique have been investigated. The tests include the miminal required TaN substrate thickness and the bias applied on both constituents in the bilayer. Electromigration tests results, obtained on via ended lines and via chain structures, for the optimized TaN/Ta bilayer barrier are compared to results on the single layer barriers of Ta and TaN. A significant improvement in electromigration performance is observed for the bilayer barrier for which the alpha-Ta phase formation was optimized.

To assess the relevance of current crowding to electromigration-induced mass transport, a test structure was designed to structurally induce and accelerate current crowding in Cu damascene lines. Electromigration experiments and quantitative finite element analysis demonstrate how current crowding can substantially enhance local atomic flux along critical diffusion paths. The resulting flux divergence leads to rapid void nucleation and growth. The observed increase in atomic flux and flux divergence is also moderately affected by the presence of Joule-heating-induced temperature gradients.

A slit-test structure is designed to structurally induce and accelerate current crowding in Cu damascene lines. Electromigration experiments and quantitative finite element analysis demonstrate how current crowding can substantially enhance local atomic flux along critical diffusion paths. The resulting flux divergence leads to rapid void nucleation and growth. In a comparison with traditional single damascene Cu Blech structures, the amount of current crowding is shown to be determined by the geometrical configuration of the test structure. Decreasing the barrier thickness or enlarging the height to width ratio of the Cu line leads to more pronounced current crowding and results in the acceleration of mass transport along the Cu/barrier interfaces.

Am important improvement in electromigration (EM) resistance was revealed upon the introduction of atomic-layer-deposited WCN barriers in dual-damascene Cu interconnects. At stress level EM failure were found to increase with WCN thickness and to be consistently superior compared to I-PVD deposited barriers. Although the voiding scenario is identical for both ALD and I-PVD barriers, a reduction of the current density exponent and the activation energy is observed for ALD. In contrast to the influence of WCN barrier thickness on the EM behaviour, the effect of specific pre-clean procedures prior to the ALD process turned out to the less pronounced.

Starting from the concept of single-damascene Blech structures, a slit-test structure was devised for the assessment of mass transport at the Cu/barrier interface. Much more compatible with standard processing, the proposed slit-test structure easily matches the sensitivity to mass transport of traditional Blech structures. Finite Element Analysis indicates the electron flow in this structure to be concentrated at the Cu/barrier interface, making it electrically very sensitive to mass transport along this diffusion path. Electrical and physical failure analysis suggest a sensitivity high enough to enable wafer-level testing of interface diffusion at user conditions.

The spin-on low-k material coated directly on the metal lines, which is called the direct-on-metal (DOM) approach, has been investigated with respect to issues about the intraline capacitance, the intraline leakage current, metal corrosion, unlanded vias, and electromigration lifetime. The results indicate that DOM can be successfully integrated with less process steps and better performance.

A magnetoresistive random access memory, based on a dynamic random access memory-like floor plan, is demonstrated for an array of magnetic memory cells. Each memory cell consists of a giant magnetoresistive spin-valve structure in series with a GaAs diode. Any single bit in the matrix can be addressed using a coincident current scheme, both for write and read operations. The integration of a series diode in the memory cell yields, for this first demonstrator, read signals of approximately 10 mV.

We describe the DRAM-like approach towards a non-volatile magnetoresistive memory integrating magnetic and semiconductor devices into one cell. The speed at which the magnetic memory signal can be read depends on many factors. An important factor is the magnetic element itself, the size, magnetic characteristics and absolute resistance. Secondly, the design of the read-out electronics is a key issue. A third determining factor is the technology in which the electronics are fabricated. Some features are indicated that are essential in optimizing MRAM in future

In this report we present the fabrication of superlattices consisting of heterogeneous magnetic GaAs:MnAs layers and InGaAs spacers with equal thickness. The magnetic and structural properties of such a superlattice are described, showing that under the appropriate annealing conditions the low-temperature grown superlattice structure is preserved and that the MnAs magnetic clusters can be formed in 2D sheets separated by thin (5-20 nm) semiconductor layers of good crystalline quality. CPP magnetotransport studies only show measurable MR at low temperatures, dominated by the dilute magnetic semiconductor Ga(Mn)As host lattice of the MnAs clusters.

This paper reports on the-structural and magnetic properties of tau MnAl/Co superlattices epitaxially grown on AlAs/GaAs by Molecular Beam Epitaxy. In tau MnAl/Co superlattices with Co layer thickness < 8 Angstrom, a strong anti-ferromagnetic coupling between the ferromagnetic tau MnAl and Co layers is found, as well as the presence of a large perpendicular magnetic anisotropy in both constituent layers, resulting in an unusually abrupt spin reversal at high fields. When increasing the Co layer thickness, the shape anisotropy in the Co layers dominates this AF coupling and the constituent layers display different magnetization directions: perpendicular (tau MnAl) and parallel (Co) to the growth plane.