In this paper, dry etched vertical nanowires (VNWs) are used in transmission line/transfer length analysis to study the contacts of gate-all-around devices for future technology nodes. VNW resistors with Mo and Pd based metal stack contacts to p-InGaAs show Schottky behavior, unlike the planar counterpart. The resistance for Mo contact is higher than Pd, however, Pd was found to form an alloy with InGaAs at temperatures as low as 190 °C, and the length of Pd diffusion into the InGaAs increased at smaller NW dimensions, hindering future scalability. The minimum extracted specific contact resistivity (ρC) values are 1.6 × 10−5 Ω cm2 (Mo) and 4.2 × 10−6 Ω cm2 (Pd) for a doping level of 1 × 1019 cm−3. An apparent dependence of ρC on the NW diameter was also observed. This has been attributed to the surface states under the un-gated region of NW devices and found to dominate at smaller diameters. An analytical model to account for such geometrical effects has also been developed and validated with technology computer-aided design simulations. The analysis presented in this paper effectively captures the 3D aspects of an NW contact at nanoscale dimensions and can be applied irrespective of the semiconductor and contact metal used.

Strain engineering in semiconductor transistor devices has become vital in the semiconductor industry due to the ever-increasing need for performance enhancement at the nanoscale. Raman spectroscopy is a non-invasive measurement technique with high sensitivity to mechanical stress that does not require any special sample preparation procedures in comparison to characterization involving transmission electron microscopy (TEM), making it suitable for inline strain measurement in the semiconductor industry. Indeed, at present, strain measurements using Raman spectroscopy are already routinely carried out in semiconductor devices as it is cost effective, fast and non-destructive. In this paper we explore the usage of linearized radially polarized light as an excitation source, which does provide significantly enhanced accuracy and precision as compared to linearly polarized light for this application. Numerical simulations are done to quantitatively evaluate the electric field intensities that contribute to this enhanced sensitivity. We benchmark the experimental results against TEM diffraction-based techniques like nano-beam diffraction and Bessel diffraction. Differences between both approaches are assigned to strain relaxation due to sample thinning required in TEM setups, demonstrating the benefit of Raman for nondestructive inline testing.

The deep levels in amorphous Ge0.5Se0.5 layers have been analyzed by Deep Level Transient Spectroscopy (DLTS). To that end, Metal-Insulator-Semiconductor (MIS) capacitors have been prepared by Physical Vapor Deposition of the films on p-type silicon substrates. A so-called quasi-constant capacitance procedure has been developed to account for the strong flat-band voltage shift of the capacitance-voltage characteristic with temperature. Applying this procedure to the as-deposited layers in the subthreshold regime reveals a dominant broad hole trap, with deep level parameters (trap concentration, hole capture cross section and activation energy) that strongly depend on the deposition conditions and the layer thickness. It is, finally, shown that the trap filling behavior does not follow the capture kinetics for simple point defects. Based on this observation, arguments are presented for an alternative analysis of the DLTS data. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

This paper shows the importance of oxygen control at the SiGe fin surface and within the gate stack. Optimized SiN liners are required to protect SiGe fins from oxidation during a flowable CVD (FCVD) densification anneal. Suppression of oxygen diffusion or scavenging from GeO via metal electrode is essential to achieve a low-D IT SiGe gate stack. By replacing HfO 2 with other dielectrics offering lower oxygen diffusivity, impact of metal electrode deposition process as well as the HfO 2 nitridation is corroborated to be related to the oxygen diffusivity. Finally, when using an embedded B-doped Si 0.4 Ge 0.6 S/D, higher channel strain in Si 0.7 Ge 0.3 than in Si p-fins is obtained as predicted by TCAD.

The electrical activity of extended defects in III-V materials, combining different analysis methods based on lifetime extraction from diode current-voltage characteristics, time resolved photoluminescence (TRPL) and deep level studies using Deep Level Transient Spectroscopy (DLTS) is reviewed. To that purpose p(+)n junction diodes have been fabricated in In0.53Ga0.47As hetero-epitaxial layers on semi-insulating InP or GaAs substrates. By depositing a strained buffer layer, the Extended Defect Density (EDD) can be varied over several decades, enabling a systematic study of their electrical impact in the same range. The defect densities are determined by High-Resolution X-ray Diffraction (HR-XRD), DLTS and Electron Channeling Contrast (ECCI) techniques. The generation and recombination (GR) lifetimes of the In0.53Ga0.47As layers become dominated by the EDs for densities above about 3 x 10(7) cm(-2), whereby the dominant GR level moves closer to the mid gap position. This is supported by DLTS investigations, showing the occurrence of specific electron traps for defective epi layers, which exhibit a capture behavior that is typical for extended defects. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

Monolayer-thin WS2 with (0002) texture grows by chemical vapor deposition (CVD) from gas-phase precursors WF6 and H2S at a deposition temperature of 450 °C on 300 mm Si wafers covered with an amorphous Al2O3 starting surface. We investigate the growth and nucleation mechanism during the CVD process by analyzing the morphology of the WS2 crystals. The CVD process consists of two distinct growth regimes. During (i) the initial growth regime, a fast and self-limiting reaction of the CVD precursors with the Al2O3 starting surface forms predominantly monolayer-thin WS2 crystals and AlF3 crystals that completely cover the starting surface. During (ii) the steady-state growth regime, a much slower, anisotropic reaction on the bottom, first WS2 layer proceeds with the next WS2 layer growing preferentially in the lateral dimensions. We propose that the precursor adsorption reaction rate strongly diminishes when the precursors have no more access to the Al2O3 surface as soon as the WS2 layer completely covers the Al2O3 surface and that the WS2 crystal basal planes and AlF3 crystals have a low reactivity for WF6 adsorption at 450 °C. Nonetheless, a second layer of WS2 starts to form before the first WS2 layer completely covers the starting surface, albeit the surface coverage of the second layer is low (<20%, after 25 min of CVD reaction). During the steady-state growth regime, predominantly the WS2 crystals in the second monolayer continue to grow in lateral dimensions up to ∼40 nm. These crystals reach larger lateral dimensions compared to the crystals in the bottom, first layer due to low reactivity for WF6 adsorption on the WS2 basal plane compared to Al2O3. Presumably, they grow laterally by precursor species that adsorb on and diffuse across the WS2 surface, before being incorporated at the more reactive edges of the WS2 crystals in the second layer. Such a process proceeds slowly with only up to 40% surface coverage of the second WS2 layer after 150 min of CVD reaction. The CVD reaction is mediated by the starting surface: WF6 precursor preferentially adsorbs on Al2O3, whereas adsorption is not observed on SiO2. Nevertheless, WS2 grows on SiO2 in close proximity to Al2O3 in 90 nm pitch Al2O3/SiO2 line patterns. Hence, functionalization of the starting surface (e.g., SiO2 with Al2O3) can provide opportunities to grow monolayer-thin WS2 crystals at predetermined locations by selective, lateral growth with tunable crystal size, even at low deposition temperatures.

A new method is proposed to enable high-throughput and high-resolution electrical atomic force microscopy in nanoelectronics. Using a reversed pathway of operation, our technique yields a shorter time-to-data (<10x), enhanced dataset statistics and nm-precise resolution; as herein demonstrated for two- and three-dimensional carrier profiling in fin structures of advanced nodes.

We have utilized the scalpel scanning spreading resistance microscopy (s-SSRM) technique in order to successfully extract for the first time 3D carrier distributions into multi-channel horizontal gate-all-around (GAA) silicon nanowires nMOS and pMOS transistors. Good correlation with DIBL characteristics of the device could be established, assessing the validity of the measurements. Compared to FinFET control samples, the results give a first explanation of the ON-current performance increase of GAA pMOS device. TCAD simulations confirm indeed that the nanowire confinement has a positive impact on SiGe:Si interface resistance.

We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to improve the performance, variability, noise and reliability behavior for junctionless (JL) vs. inversion-mode (IM) vertical FETs built with an RMG scheme. The latter enables a novel concept to introduce stress in VFETs for enhanced mobility with up to a19% higher I ON predicted. SiGe/Si pillars and self-aligned spacers offer a solution to gate vertical (mis)alignment towards the S/D. As MRAM selector, VNS FETs can allow substantial area reduction (64% for 2VNS per cell; 3nm node design rules) vs. finFET based cells, with smaller read/write energy consumption and latency times.

We report on the uniform selective area growth of InAs and GaSb by metal-organic vapor phase epitaxy on a patterned shallow trench isolation SiO2/Si 300 mm template. High-quality InAs fins are realized via direct InAs nucleation on Si in the trenches. 60° interfacial misfit dislocation arrays formed along the {111} oriented InAs/Si interfaces accommodate most of the lattice mismatch such that threading dislocation generation from residual strain is minimized. GaSb grown on a thick GaAs buffer (partial filling of the trench) suffers from twin formation. The twin density is found to decrease with increasing growth temperature. To maximize the volume of low-defect density material inside the trench, the GaSb growth is initiated as close as possible to the trench bottom. Therefore, uniform high-quality GaSb fins are grown on a very thin low-temperature GaAs and the newly developed InAs seed in the V-groove. High-resolution x-ray diffraction reciprocal space maps show that the InAs and GaSb fins are nearly completely relaxed. The resistivity of undoped and n-doped InAs and undoped and p-doped GaSb fins is measured on as-grown material by micro-4-point-probe without the need for additional complicated device processing. The values are compared to those required for devices as presented in modeling papers. The result is encouraging for the ultra-large-scale integration of vertical nanowire III-V (tunnel) field-effect transistor on 300 mm Si.

An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at I OFF =3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at -0.5 V DD . The temperature dependent study of I D,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.

In semiconductor technology, mechanical stress is one of the principal performance boosters available to device engineering for the development of state-of-the-art logic transistors. Currently available strain characterization techniques are either destructive or have low spatial resolution because they use broad beams (Raman, X-ray diffraction). Fast, accurate and non-invasive stress measurements beyond the diffraction limit remain a challenge. However, it was recently found that the geometry of the structure itself can be used as an enhancement tool to bring out the relevant Raman signals from the region of interest. The theoretical understanding of the effect was fine-tuned such that the concept can be applied on the materials and structures of choice. Recently a strategy was developed to extract detailed and quantitative stress values of deep sub-wavelength semiconductor structures. The approach enables the quick and non-invasive quantitative characterization of stress inside CMOS devices of the next generation.

Defects in Ge0.947Sn0.053 layers grown using molecular beam epitaxy on (001) Si substrates with 4.9% mismatch are investigated using optical, scanning, and transmission electron and atomic force microscopies. It is shown that the strain relaxation occurs via the introduction of 90° misfit dislocations of short length, at the Ge0.947Sn0.053/Si interface. An irregular morphology in the form of mounds is observed on the surface of epitaxial Ge1−xSnx (0.031 ≤ x ≤ 0.093) and is found to be associated with carbon impurities at the hetero-interface. A low-cost and fast defect selective wet etching technique is described to determine the etch pit density in epitaxial Ge1−xSnx with a low Sn content (≤5.3%). On the basis of etch pit morphology, different defects, e.g., dislocations, stacking faults, and crystal originated particles, are distinguished.

Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology nodes as they can offer better electrostatics than FinFETs. In this paper, we show another advantage of strained Ge NW pFET over strained Ge FinFET, which lies in the preservation of Strain-RelaxedBuffer (SRB)-induced strain through fin cut and S/D recess. This benefit comes from the presence of the sacrificial SiGe layers. Lowering the Ge concentration in the SiGe sacrificial layer is a way to further suppress the strain loss. Furthermore, a comparison of Ge NW pFETs integrated on Ge SRB and SiGe SRB reveals that SiGe SRB provides a huge advantage not only in the strain engineering but also in I-OFF control. These are key enablers in maximizing the performance while minimizing the I-OFF of strained Ge NW pFETs.

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB.

ALCVD ZrO2 thin films as deposited and after annealing at different temperatures in oxygen atmosphere are characterised by cross sectional high resolution transmission electron microscopy, plan-view dark-field imaging and electron diffraction.

With further down-scaling below 0.25mum technologies, CoSi2 is replacing TiSi2 because of its superior formation chemistry on narrow lines and favourable stress behaviour. Shallow trench isolation (STI) is used as the isolation technique in these technologies. In this study, convergent beam electron diffraction (CBED) measurements and finite element modelling (FEM) are performed to evaluate the local stress components in the silicon substrate, induced in STI structures with a 45 nm or a 85 nm CoSi2 silicidation. High compressive stresses in the active area and tensile stress around the trench corners are observed.

This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, I on =500μA/μm at I off =100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si 0.3 Ge 0.7 SRB.

The performance of heterogeneous 3D transistor structures critically depends on the composition and strain state of the buffer, channel and source/drain regions. In this paper we used an in-line high resolution x-ray diffraction (HRXRD) tool to study in detail the composition and strain in selectively grown SiGe/Ge fin structures with widths down to 20 nm. For this purpose we arranged fins of identical dimensions into larger arrays which were then analyzed using an x-ray beam several tens of micrometers in size. Asymmetric reciprocal space maps measured both parallel and perpendicular to the fins allowed us to extract the lattice parameters in all three spatial directions. Our results demonstrate an anisotropic in-plane strain state of the selectively grown SiGe buffer in case of narrower fins with significantly reduced relaxation in the direction along the fin. This observation was verified using nanobeam electron diffraction, and is explained based on the reduced probability for dislocation half-loops to evolve in trenches narrower than a few times the critical radius. Moreover, we introduce and discuss in detail a methodology for the determination of the composition in case of an anisotropic in- plane strain state which differs from the procedure commonly used for blanket layers. Our findings verify the importance of in- line HRXRD measurements for process development and monitoring as well as the fundamental study of relaxation and defect formation in confined volumes.

As Si-based electronic devices are approaching their projected scaling limits, layered two-dimensional (2D) materials such as transition metal dichalcogenides (TMDs) are extensively studied as potential new channel materials and fundamental building blocks of emerging sensors and devices.[1-2] In this context, MoS2, WS2 and WSe2 to name a few, are now available for deposition trough different top down approaches. However, their outstanding properties are often degraded during the fabrication processes required for the device integration. For example, the selective growth of 2D TMDs their patterning and the electronics properties fine tuning still remain elusive. Here we report on electrical atomic force microcopy (AFM) and beam analysis techniques which are used to develop a framework of analysis for 2D materials. The latter is applied to understand the local properties of MoS2 comparing pristine material and structures which are selectively grown and patterned.[3] Different growth techniques are investigated. After modelling the tip-sample contact system, we assess the impact of the plasma-induced damages combining the electrical AFMs and Auger emission spectroscopy. We study the local electrical properties of grain boundaries and their transport respectively in pristine and patterned structures for FET devices by conductive atomic force microscopy (C-AFM). [1] G. Fiori, F. Bonaccorso, G. Iannaccone, T. Palacios, D. Neumaier, A. Seabaugh, S. K. Banerjee, and L. Colombo, “Electronics based on two-dimensional materials,” Nat. Nanotechnol., vol. 9, no. 10, pp. 768–779, 2014. [2] Desai, S. B., Madhvapathy, S. R., Sachid, A. B., Llinas, J. P., Wang, Q., Ahn, G. H., Javey, A. (2016). MoS 2 transistors with 1-nanometer gate lengths, 354(6308), 2–6. [3] Chiappe, D., Asselberghs, I., Sutar, S., Iacovo, S., Afanas’Ev, V., Stesmans, A., … Thean, A. (2016). Controlled Sulfurization Process for the Synthesis of Large Area MoS2 Films and MoS2/WS2 Heterostructures. Advanced Materials Interfaces, 3(4), 1–10.