A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified R-S formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 mu m process to fabricate stacked inductor with various sizes and types. All the measured data are extracted from a silicon device based on a physical layered test system (PLTS). The predicted and measured S-parameter results show excellent correlation in terms of performance for frequencies up to 15 GHz. A high-Q on-chip active inductor is demonstrated using a multiple turns stacked inductor.

PurposeTo show new design methodology of low power circuit design (Low Power Critical Voltage Transition Logic – LPCVTL) over the conventional CVTL methodology. The comparison is in terms of speed, area and power consumption.Design/methodology/approachThe new design employs feedback mechanism with a different clocking methodology to overcome high static power dissipation of conventional CVTL design.FindingsLPCVTL has lower power dissipation property as compared to the conventional CVTL design through the observation of the simulated results of an inverter chain and half adder designs. LPCVTL power dissipation is about eight times smaller than the conventional CVTL.Research limitation/implicationsThe desired clock frequency is limited by the output signal response.Originality/valueLPCVTL is an alternative to dynamic digital IC design methodology which has high speed advantage while maintaining low power consumption.