A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified R-S formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 mu m process to fabricate stacked inductor with various sizes and types. All the measured data are extracted from a silicon device based on a physical layered test system (PLTS). The predicted and measured S-parameter results show excellent correlation in terms of performance for frequencies up to 15 GHz. A high-Q on-chip active inductor is demonstrated using a multiple turns stacked inductor.

A miniaturized multi-layer symmetrical stacked balun designed and fabricated in a commercial CMOS technology are presented. The measured performance of the compensated single-ended drive balun, in good agreement with simulation, covers the frequency range of 800MHz similar to 2.5GHz with the amplitude mismatching less than 0.4dB and phase errs less than 3.2 degrees. The die size of the balun is only 270 mu mX270 mu m.

This paper presents a 6th order RF bandpass filter using low-voltage based on active inductor. In the filter, a design technique for a high-Q CMOS active inductor operating in the RF-band is described. Simulated performance presented is shown that the center frequency of filter using a 0.25-mum CMOS process can be operated at the 2.05-2.45 GHz frequency band under a 1.8V power supply and suitable for multiband wireless applications and RF system on-chip

In this paper, we proposed two baluns, a compact balun and a compact balun with imbalance compensation; both are implemented using the one-poly six-metal (1P6M) 0.18 μ m CMOS process. Both baluns have good performance from 4 to 10 GHz, and consume less silicon area due to their compact structure. The self-resonant frequency is increased by properly selecting metal layer for each spiral winding. The compact balun has a magnitude imbalance of 1 dB and a phase imbalance of 4.6 degree from 4 to 10 GHz. With the imbalance compensation, the balun has a magnitude imbalance of 0.6 dB and a phase imbalance of 1.1 degree from 4–10 GHz. Much better results have been achieved for the compact balun with our proposed imbalance compensation method. Both baluns can be used to perform both single-ended/differential and differential/single-ended conversions in different configurations.

In this paper, a 2.45GHz PA combined with a T/R switch has been designed and fabricated using a 0.35/spl mu/m SiGe process. It shows a very good performance of about 20dBm output power, 18.3% power efficiency including the insertion loss of T/R switch, 1.5dB insertion loss in the receiving mode, and more than 30dB isolation. It's applicable to 2.45GHz ISM (industrial, scientific, and medical) applications.

A novel methodology for reducing the phase noise of a cross-coupled LC tank VCO is presented, verified and measured. The fundamental relationship between the phase noise and the channel length of the cross-coupled MOS transistors is derived, and an optimum channel length of MOS transistors is indicated for a cross-coupled LC tank VCO with the lowest phase noise. A 2 GHz LC tank VCO is designed by this methodology and fabricated by 0.18 /spl mu/m CMOS technology. The phase noise is -103.3 dBc/Hz at 100 kHz offset frequency and -118.9 dBc/Hz at 600 kHz offset with low-power consumption around 3.15 mW. The best FOM value of 186 is achieved compared to the reported 2 GHz VCO. The tuning range is 14% at a center frequency of 2.05 GHz.

The paper presents the design and realization of a novel 23 GHz sub-harmonic mixer using an input diplexer. The measured performance of the 23 GHz SHM is as follows: RF of 22.1-23.5 GHz; IF band larger than 1.4 GHz; LO working frequency can be selected at any frequency in the band of 1 GHz at the center of 10 GHz. The conversion loss is 8.7 dB. The isolation among LO, IF and RF is greater than 30 dB. The design techniques are attractive for designing a high port isolation sub-harmonic mixer.

This paper describes a new non-sequential linear phase detector using a standard 0.18 mu m CMOS process for high-speed clock and data recovery applications. The new phase detector avoids using DFFs or D-latches in order to achieve high operating speeds up to 10 Gbit/s. Its circuit structure is much simpler than the existing half-rate 10 Gbit/s phase detectors reported so far. Consisting of I delay cell, 2 XOR gates and 1 AND gate, the proposed PD consumes 34.58 mW. It exhibits a linear characteristic for low jitter operation and avoids half-cycle skew problem inherent in the conventional linear phase detectors. The simple structure of the proposed PD also has the advantage of lower power consumption compared with other PDs reported in the literature.

A novel two-order bandpass filter (BPF) is proposed. The parallel coupling paths as well as similar zero point generation mechanism for the fundamental frequency and the first spurious frequency give the filter three controllable finite zero points in the stopband without adding any extra elements. Good skirt selectivity and controllable stopband characteristics can be achieved simultaneously.

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.

A spurs reduction fractional-N frequency divider with a frequency range which is 3.5 times larger than that of a conventional fractional-N divider is presented in this paper. A 1.2-GHz quadrature voltage-controlled oscillator (VCO) is designed as the input source of the frequency divider. The circuit was fabricated using the 0.25-mu m CMOS technology. The power consumption of the frequency divider and the quadrature VCO are 3 and 6 mW, respectively, at a 2-V supply.

A novel imbalanced phase-switching technique for high-speed prescaler design is investigated. Different from the traditional 50% duty cycle phase-switching technique, it uses 1/4 duty cycle phases to increase the delay budget in dual-modulus control. It significantly improves the performance of the prescaler in terms of operating frequency and power consumption, compared with the existing 50% duty cycle phase switching technique. This improvement makes it applicable to ultra-high-speed CMOS prescaler design. Two prescalers, with 2-to-1 and 4-to-1 phase switching are designed using this technique. The proposed 2-to-1 phase switching divide-by-7/8 prescaler with simplified topology using the Chartered 0.18 micron CMOS process is capable of operating from 1.5 GHz to 6 GHz with a 7 mW power consumption from a 1.8 V supply. Such operating frequency ranges cover most of the wireless LAN standards. The prescaler with 4-to-1 phase switching can work from 2 GHz to 10 GHz with a power consumption of 15 mW from a 1.8 V supply. The proposed technique is promising in relation to multi-GHz CMOS prescaler design because it eliminates the design trade-offs associated with other techniques.

A modified model for RF interconnect bends on lossy substrate in CMOS technology is presented. The model parameters are extracted directly from the on‐wafer S‐parameter measurements. The accuracy is verified up to 20 GHz by the measurements of the test structures. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 45: 170–173, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20760

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-/spl mu/m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 /spl mu/m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.

The design of a high-speed wide-band high resolution programmable frequency divider is investigated. A new reloadable D flip-flop for the high speed programmable frequency divider is proposed. It is optimized in terms of propagation delay and power consumption as compared with the existing designs. Measurement results show that an all-stage programmable counter implemented with this D flip-flop using the Chartered 0.18 µm CMOS process is capable of operating up to 1.8 GHz for a 1.8 V supply voltage and a 5.8-mW power consumption. By using this counter, an ultra-wide range high resolution frequency divider is achieved with low power consumption for 5-6-GHz wireless LAN applications.

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.

A novel RFCMOS process monitoring test structure has been proposed for the first time in this paper. Excellent agreement in DC and RF characteristics has been observed between conventional test structures and the new process monitoring test structure for both n and p MOSFETs of different device dimensions. This new layout approach can be extended to other devices such as MIM capacitors, diodes, MOS varactors and interconnects.

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-/spl mu/m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier.

The design of a 10-GHz voltage-controlled oscillator (VCO) for synchronous optical network (SONET) applications is presented in this paper. The circuit is fabricated in 0.18-mum RF CMOS process and it has a phase noise of -95 dBc/Hz at 1-MHz offset and a very low power consumption of 2.5 mWfrom a 1.8-V supply, excluding the output buffers. The effect of supply voltage on the VCO tuning range and the ways to optimize VCO operation in the SONET system are also investigated. (C) 2004 Wiley Periodicals, Inc.