This article presents an 88.2-to-102.5-GHz phase-locked signal source based on a phase-locked loop (PLL) cascaded with a frequency octupler. The underlying ripple-canceling phase detector (RCPD) provides a baseline framework for structural suppression of the PLL reference spur, whereas pulsewidth modulation (PWM) is introduced as the key enhancement to realize the proposed pulsewidth-modulated RCPD (PWM-RCPD). By shortening the effective current-injection interval, the PWM-RCPD further suppresses both the residual reference spur and the intrinsic in-band phase noise (PN) contribution of the phase detector. To mitigate deterministic mismatch in the dual-path ripple-canceling structure, a one-time calibration scheme is employed. The same RCPD principle is further extended to implement an automatic frequency control (AFC) loop for frequency detection. In addition, a complementary quadrature injection-locked frequency quadrupler (FQ) is adopted to enlarge the locking range (LR), with coarse frequency alignment assisted by the AFC. Fabricated in a 28-nm CMOS technology, the proposed signal source achieves a reference spur of -77.8 dBc, a frequency tuning range (FTR) of 88.2-102.5 GHz (15%), and an integrated jitter of 67.6 fs(rms) from 1 kHz to 100 MHz, corresponding to a jitter-power figure-of-merit of -247.4 dB.

This article proposes a millimeter-wave (mm-wave) low-noise amplifier (LNA) with tri-coil transformer-based G(m) -boosting and noise suppression technique. In the proposed work, a novel codirectional (co-dir) tri-coil transformer (TF) is utilized to enhance the transconductance ( G(m) ) of the transistor and suppress transistor thermal noise. Moreover, the proposed single-ended LNA contains only one active device per stage, which introduces minimum noise. The proposed LNA provides a high gain, reduced noise figure (NF), and good linearity. Fabricated in standard 28-nm CMOS technology, the measured results show the proposed LNA exhibits a peak gain of 19.8 dB at 36.75 GHz and a 3-dB bandwidth from 33.2 to 43.2 GHz. The measured NF is 2.17-2.85 dB within the operating frequency range. The in-band input 1-dB compression point (IP 1dB ) is -13.6 dBm, and the input-referred third-order input intercept point (IIP3) is -3.8 dBm at 37 GHz. It consumes 14.9 mW of power from a 0.9-V supply voltage and occupies a die area of 0.27 mm(2).

Millimeter-wave (mmW) phase-locked loops (PLLs) prefer large loop bandwidth for suppressing more voltage-controlled oscillator (VCO) phase noise, which, in turn, degrades the level of rejection to reference spur. This article proposes a complementary mixing phase detector (CMPD) to relax the above tradeoff through the spur compensation technique. Distinct from traditional RC filtering, the CMPD realizes spur reduction by mutual harmonic rejection whose effectiveness is enhanced by a foreground calibration. It also neutralizes charge injection and clock feedthrough without consuming extra power, while enabling frequency detection and lock detection. Fabricated in a 28-nm CMOS technology, the PLL achieves a frequency tuning range (FTR) of 28.8-to-43.2 GHz, - 78.5-dBc reference spur, and an rms jitter of 79.8 fs(rms) (from 10 kHz to 100 MHz), with a jitter-power figure-of-merit (FoM) of - 250.0 dB.

Ring voltage-controlled oscillator (VCO) based PLLs have several advantages over LC-VCO based PLLs, like smaller chip area, wider frequency tuning range and multi-phase output signals. However, the inferior jitter/phase noise of ring VCOs has always been the bottleneck of the overall PLL jitter/phase noise performance. To suppress ring VCO's phase noise, feedforward phase noise cancellation (FFPNC) techniques [1]–[4] and feedback phase noise cancellation (FBPNC) technique [5] are widely researched. However, most FFPNC and FBPNC based structures require numerous additional blocks, like complicated phase noise extraction circuits, long voltage-controlled delay line, or additional clock generation circuits, which consumes significant extra area and power. In order to suppress the phase noise of the ring VCO with minimal area and power consumption, this paper proposes a dual-path sub-sampling PLL (SSPLL) architecture incorporating an FBPNC technique. The SSPLL's bandwidth is extended with a compensated phase margin due to the proposed FBPNC technique, as a result, the in-band phase noise contributed by the ring VCO is effectively reduced.

This paper proposes an inductorless wideband common-gate (CG)-common-source (CS) noise-cancelling (NC) low-noise amplifier (LNA) with current reuse (CR) for ultra-low voltage (ULV) application. In the conventional NC LNA with CR, to reuse the DC current of the auxiliary amplifier, three transistors are stacked in a single branch, leading to a reduced voltage headroom. Moreover, additional inductor and capacitors are required, resulting in a large silicon area. In the proposed work, the DC current of the auxiliary amplifier can be reused without using any inductor. Meanwhile, only two transistors are stacked in a single branch, making it suitable for ULV application. Fabricated in 28 nm CMOS, this work exhibits a voltage gain of 20 dB with a 3-dB bandwidth of 0.2 to 2.85 GHz, a minimum NF of 2.9 dB at 1.7 GHz and an IIP3 of -12.3 dBm at 1 GHz. It consumes 1.74 mW from a 0.6 V supply and occupies a very compact die area of 0.0048 mm $^{2}$ .

An inductorless wideband auxiliary-path-free noise-cancelling (NC) low-noise amplifier (LNA) with current reuse is proposed. In conventional NC technique, the noise of the main amplifier is cancelled by adding an auxiliary amplifier, which introduces additional noise and consumes extra power. In the proposed work, the noise of the main amplifier can be suppressed at zero theoretically while no additional auxiliary amplifier is required. Moreover, the complementary current reuse structure is exploited in this work for power reduction. Fabricated in 28 nm CMOS, the LNA exhibits a voltage gain of 17.7 dB with a 3-dB bandwidth of 0.25 to 2.7 GHz, a minimum noise figure (NF) of 2.9 dB at 1.2 GHz and an IIP3 of 6.8dBm at 1 GHz. It consumes 1.59 mW from a 0.6 V supply and occupies a very compact die area of $0.0076 \mathbf{~ m m}^{2}$.

High data throughput and wideband network communications demand high-speed (several to tens of GS/s), moderate-resolution (6–10b) ADCs. The emerging time-domain ADC (TD-ADC) has been gaining more interest because of its energy efficiency and area efficiency [1], [2], providing a promising solution for high-speed architectures. However, the speed superiority of the TD-ADC, enabled by time-domain quantization, has not been sufficiently leveraged due to the long waiting time allocated for multiple bit decisions, which consumes the conversion period [1]–[3]. In addition, the voltage-to-time converter (VTC) front end suffers from linearity degradation at high frequencies (10GHz) [4]. In this work, we have implemented an asynchronous successive approximation (ASA) time-to-digital converter (TDC), significantly improving the throughputs through time-domain pipeline operation. Furthermore, reliability is guaranteed without adding extra delay in the clock path due to the inherent robust synchronization scheme of ASA. On the other hand, the VTC nonlinearity is compensated by optimizing the reference delays in the ASA TDC, utilizing the least-mean-square (LMS) tuning at the circuit design stage. To demonstrate the speed superiority of the TD-ADC, a prototype single-channel ADC was fabricated in 28nm CMOS, achieving 36.4dB SNDR, 58.9fJ/conv.-step figure-of-merit (FoM) at 10GS/s with Nyquist input, occupying 0.009mm2 active area, and presenting the fastest single-channel speed compared to other state-of-the-art of ADCs with 8b resolution.

This paper proposes a dual-feedforward-based noise-cancelling (NC) technique, where the noise contribution of the auxiliary amplifier is proportional to its transconductance, allowing for simultaneous current and noise reduction. This technique is used to implement a low-noise transconductance amplifier (LNTA) tailored for current-mode receiver. Moreover, the complementary NMOS and PMOS configuration is employed to improve the third-order linearity performance by attenuating the second-order distortion. Fabricated in TSMC 28nm CMOS, the differential inductorless LNTA achieves an $S_{21}$ of 10. 2dB with a 3-dB bandwidth of 0.25 to 3. 7GHz, a NF of 2. 4dB at 1. 4GHz and an IIP3 of 4.1dBm at IGHz. It draws 6. 6mA from a 1. 2V supply, occupying a compact active area of 0.021mm 2 .

A Ka-band millimeter wave (mmW) integer-N phase-locked loop (PLL) exploiting a novel current-reuse coupled mixer (CRCM) phase detector (PD) is proposed. Aiming to attenuate the reference spurs in the PLL, the CRCM PD is realized by a pair of coupled mixers folded to each other, achieving mutual spur compensation without consuming extra power or narrowing the PLL loop bandwidth. A mmW signal source is constructed by a two-stage PLL followed by a frequency tripler. Realized in a 28 nm CMOS process, the signal source attains a locking range of 29-39.3-GHz, maximum reference spur of −73.7 dBc, and 160.6 fs rms integrated jitter (integrated from 1 k to 100 MHz). It consumes 14.2 mW power and occupies an active area of only 0.1 mm 2 , achieving a figure of merit (FoM) of −244.4 dB when using a 150-MHz reference.

This article presents a single-channel voltage-scalable 8-GS/s 8-b time-domain analog-to-digital-converter (TD-ADC). It breaks the speed limit of traditional TD-ADC by leveraging asynchronous pipeline successive approximation (APSA), which reduces the quantization period to approximate one-stage time-domain comparator decision time. A co-design methodology of voltage-to-time converter (VTC) and time-to-digital converter (TDC) is proposed to optimize the ADC linearity without increasing the complexity or power consumption, reducing the linearity request of VTC. In addition, concurrent charge redistribution and voltage pull-up is deployed in the VTC, supporting the rail-to-rail input and enabling voltage scalability. The TD-ADC is fabricated in 28-nm CMOS and occupies an active area of 0.011 mm2, demonstrating 39.2-dB signal-to-noise-distortion ratio (SNDR) and 56.1-dB spurious-free dynamic range (SFDR) at 0.9 V, 8-GS/s with 85.3-mW power dissipation and 37.6-dB SNDR and 56.3 dB SFDR at 0.7 V, 5.05 GS/s with 23.1-mW power dissipation, achieving 143.1- and 74.3-fJ/conv.-step Nyquist Walden figure of merit (FoMW), respectively.

This brief proposes a broadband noise-cancelling (NC) common-gate (CG)-common-source (CS) low-noise amplifier (LNA) with a passive network to improve the gain and noise performance simultaneously. In the CG-CS LNA with active feedforward, a current-bleeding (CBLD) circuit is required to provide the required DC current of the auxiliary amplifier, which introduces additional noise. In the proposed work, by adding a passive network at the output, the noise of the CBLD circuit can be made negligible. Moreover, the passive network also provides the shunt peaking to facilitate the gain and noise performance over the desired band. Fabricated in TSMC 40 nm CMOS technology, the measured results show the proposed LNA exhibits a gain of 16.5 – 19.5 dB, a noise figure (NF) of 3.2 – 5.2 dB from 2 to 12 GHz and an IIP3 of −3.5 dBm at 6 GHz. It consumes 9 mW from a 1.2 V supply and occupies a very compact die area of 0.092 mm2.

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs rms at 40.96 GHz and 122 fs rms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW.

In designing a mm-wave ultra-wideband pulse-Doppler radar IC, one of the main challenges encountered is to reduce the high power consumption of the circuitries in the IC. A direct-RF receiver can be used in the radar’s design to reduce the radar’s power consumption. However, a digitizer that can directly digitize mm-wave ultra-wideband radar pulses is needed to implement such a receiver. This work presents the design of such a digitizer, which comprises several multi-pass sub-ADCs that operate together. Each multi-pass sub-ADC works fundamentally like a flash ADC but comprises one comparator only. A test chip containing a 6-bit prototype of the digitizer is fabricated in a 40 nm CMOS technology. The prototype consumes 19.7 mW when operated at 4 GSa/s and can operate with input signal frequencies of up to 64 GHz while achieving a −1.7/−6 dBFS SNDR of 21.1/22.8 dB at 60 GHz (the corresponding FoM is 532/434 fJ/c-s). The digitizer has a relatively high effective parallel-equivalent input impedance at 60 GHz, which, in a radar IC implementation, allows it to be driven with a relatively low power-consuming 60 GHz RF buffer. These are achieved without the digitizer being fabricated in a much more advanced technology node.

A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters’ PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal’s pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm 2 active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving −56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW.

This paper proposes a low-power multi-mode injection-locked transmitter (TX). A negative-transconductance active-inductor-based oscillator for the multi-mode modulations (e.g., ASK/FSK/BPSK) is designed to cover wide frequency bands, e.g., 400 MHz, 800 MHz, and 915 MHz. By making use of the injection locking technique, the phase noise of the active-inductor-based oscillator is lowered to the level that is close to the “clean” incident signal. To reduce the power consumption while providing operating flexibility, the TX is digitally controlled to switch the ASK/FSK/BPSK modulations. The proposed TX is fabricated in a 65-nm CMOS technology with a nominal supply voltage of 1 V. The measurement results show the TX prototype achieves the maximum data rate of 1 Mb/s with an output power of -12dBm under a 2-mW power consumption.

Recently, there is an increasing demand for better in-band(IB) and out-of-band(OOB) linearity for sub-6GHz applications [1 – 3]. To achieve high linearity, one solution is to utilize current-mode direct conversion [1]. In this architecture, the low-noise amplifier (LNA) acts as a transconductor, which avoids large voltage gain, thus achieving high linearity. Another solution is to employ mixer-first architecture [2,3]. This kind of receiver starts with a passive mixer, which avoids any possible voltage gain brought by the LNA and shows improved tolerance to the blockers. However, unlike the current-mode architecture, its transimpedance-amplifier (TIA) input is not a virtual ground, but a high-impedance node, for input matching purpose [2]. Meanwhile, to achieve better NF, noise-cancellation techniques are widely used in different architectures to improve the noise performance [4,5], achieving sub-1dB NF at 1GHz [4] and 1.75dB NF at 5GHz [5]. However, both receivers are with LNA-first architecture, which limits their linearity.

The noise figure (NF) of the low-noise amplifier (LNA), located at the forefront of wideband receivers, directly influences the total NF of the receiver. A popular approach to suppress the noise of the input transistor to decrease the LNA NF is to utilize a noise-cancelling (NC) technique, where the main amplifier provides input matching, while the auxiliary amplifier removes the noise of the main amplifier [1]. In this scenario, the common-gate (CG) common-source (CS) NC LNA has been widely investigated because it features simultaneous noise and distortion cancellation. To achieve a NF of 3dB, the CG-CS LNA in [2] consumes 15.4mA. By employing the $g_{m}$ -boosting technique, a NF of 3.5dB is achieved in [3] while consuming 7.5mA. Benefiting from the current reuse technique, the current dissipation in [4] is reduced to 4.5mA with a NF of 2.09dB. For these reported works, the noise contribution of the auxiliary amplifier dominates the NF. However, the noise factor contributed by the auxiliary amplifier is inversely proportional to its transconductance $(g_{m})$; hence, the noise contribution of the auxiliary amplifier can only be reduced by increasing $g_{m}$ at the cost of current dissipation, rendering the NC LNA a power-hungry component of a wideband receiver.

A 0.6 V voltage-to-time converter (VTC) has been presented in this work for the emerging energy-efficient time-domain circuits and systems. The proposed VTC supports a rail-to-rail input by leveraging shrink sampling with two cascaded voltage sampling and charge sharing switches, breaking the tradeoff between linearity and input range of the traditional VTC and enabling low voltage operation. The charging current source is adjustable to calibrate the VTC gain variation. In addition, a 4-bit tunable delay buffer is inserted at the output stage to calibrate the VTC time offset, enhancing the PVT performance. By resizing the push-pull inverters’ PMOS/NMOS size ratio in the output buffer chain, the jitter contribution from buffers has been reduced. It also recovers the signal’s pulse width consumed during the voltage-time conversion, facilitating the time signal processing following VTC. Designed and fabricated in 28 nm CMOS, the prototype VTC occupies a 0.0012 mm2 active area. Measurement results show that the VTC can run up to 4 GHz at a 0.6 V power supply, achieving −56.4 dB total harmonic distortion (THD) with Nyquist input and consuming 2.1 mW.

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer- $N$ phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a −75-dBc reference spur, −101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 kHz–100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer- $N$ phase-locked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.