A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits.< >

Reducing power dissipation after technology mapping by structural transformations. Circuit activity based logic synthesis for low power reliable operations. " IEEE Advanced Automatic test pattern generation and redundancy identification techniques. circuit design using synthesis and optimization. On average power dissipation and random pattern testability of CMOS combinational logic networks. Low power state assignment targeting two-and multi-level logic implementations. Efficient estimation of dynamic power dissipation under a real delay model. Power efficient technology decomposition and mapping under an extended power consumption model. A. Sangiovanni-Vincentelli. " NOVA: State assignment of finite state machines for optimal two-level logic implementations. On computing and approximating the Observabil-ity Don't Care Set. Synthesis of multiple-level logic from symbolic high-level description languages. Low-power driven technology mapping under timing constraints " Proceed-Trading speed for low power by choice of supply and threshold voltages. " A modified approach to two-level logic minimization. Logic level power estimation considering spatio-temporal correlations. Information theoretic measures for energy consumption at register transfer level.LP: A system for power minimization using architectural transformations. 51 The definition for deep and shallow regions is implementation dependent. However experimental results show that in a network that is decomposed into 2-input gates, taking into account Reconvergant regions that span over 5 levels capture a significant part of the spatial correlation at the input of nodes in the network. In POSE an option is available for using semi-local BDDs for computing node signal probabilities. As the network is being optimized, the network structure is modified and therefore the definition of semi-local BDDs for each node will change. Therefore , if an optimization step changes the network structure drastically, the node switching activity values should be recomputed so that the new activity values reflect the new structure of the network. It should also be noted that for small networks, using global BDDs provides a more efficient and exact technique for computing the signal probabilities. This is mainly due to the overhead of computing the semi-local BDDs for each node. For larger size networks, however, the use of semi-local BDDs will result in significant speed up during power estimation. 7 Acknowledgements The authors would like to thank Chi-Ying Tsui for helpful discussions.level logic minimization using implicit don't cares. " IEEE TransFigure 21. Reconvergent fanout regions. 50 This correlation may be present even if primary inputs are spatially uncorrelated. Under these conditions, the spatial correlation at the immediate fanins of a node n is …