A multiscale technology computer-aided design (TCAD) simulation methodology is presented to calculate the intrinsic transit time of InP double heterojunction bipolar transistors (DHBTs). A 2-D hyd-rodynamic (HD) simulator is employed to produce the dc characteristics and electrostatic potentials of the selected devices. Utilizing the cuts of the obtained potential profiles as inputs, a 1-D full-band, atomistic quantum transport (QT) solver is then deployed to determine the ballistic electronic transport properties of these components. The transit times of DHBTs based on InGaAs/InP and GaAsSb/InP technologies are finally investigated with the proposed approach. Good qualitative agreements are observed with the experimental measurements. The observed underestimations of the experimental transit times are justified with the physics-based compact model HiCuM, thus providing a basis for structure and performance optimizations toward real terahertz transistors.

This paper presents a methodology for compact model evaluation and validation at circuit level for RF and mm-wave applications. Accurate compact models are a prerequisite for efficient circuit design but currently modeling engineers lack of suitable verification procedures. In this work we detail a methodology to fulfill these requirements together with circuit examples, starting from the simplest differential pair to the most advanced four stage differential LNA working at 220GHz. It is shown that a complete hierarchy of validation circuits (from the simplest circuit to the most complex) provides a new perspective with respect to the crucial task of model qualification but also directions for future compact model developments.

determination methods for the emitter resistance of bipolar transistors are reviewed and evaluated with respect to the constraints introduced by modern SiGe:C HBT processes with f(MAX) reaching 500GHz [1]. Maximum transistor performance is obtained at ever higher current densities, involving huge self-heating effect which dramatically degrades the accuracy of existing methods. A new parameter extraction procedure is presented and compared to existing solutions. Finally, a simple methodology to correct self-heating effects is proposed, which advantageously increases the accuracy of emitter resistance determination under high self-heating conditions.

This paper presents a status of the HICUM model development activities (within the DOTFIVE project) for future technologies. Physics based scalable model libraries are realized for two of the most advanced SiGe:C HBT processes currently available. The parameter extraction methodology is described via two meaningful examples. Measurement and simulation comparisons are shown.

This paper presents an investigation of the coupling between probe tips and wafer surface through EM-simulation and compares the simulation results to measurements. It is pointed out that the results are very dependent on the adjacent structures lying under the probe tips. Different solutions are analyzed to master and/or reduce the coupling and ensure reproducibility.

mm-Wave applications claim for accurate and reliable device models for their very high frequency operation range. This is not possible without any representative measurement of the intrinsic device performances especially HF small-signal measurements. In this paper we determine major parasitic contributions of regular HF test structures. Parasitic investigation goes from the probes down to the transistor. Original dummies are described and HF/DC measurements are presented and analyzed. Based on this limited set of structures a scalable de-embedding approach is described. To account for DC/HF parasitics, a sub-circuit is proposed for modeling purpose.

For device modelling purposes, the geometry dependence of the external collector resistance has been investigated. Firstly, the collector resistance is split into a perfectly 1D vertical resistance and a 2D horizontal contribution. Using specific test structures and DC measurements, geometry independent parameters are then extracted. An analytical scalable formula based on Fourier techniques finally computes both components for a given geometry by taking into account the current distribution in the horizontal layer. This new method is applied to a double poly BiCMOS technology and results are discussed.

V DD reduction in advanced CMOS IC's push for reduced temperature stability spread of bipolar based BGR. To achieve this goal, a reliable extraction methodology for I C temperature coefficient is detailed. Based on corner lot measurements, a worst-case bipolar model is built. Bandgap circuit measurements are finally compared to statistical simulations.

Based on different geometries of bipolar transistors, a new scalable method to determine the parasitic capacitances is presented. The total capacitance measured from cold S parameters could be split in an area junction capacitance, a peripheral junction capacitance and a constant oxide contribution. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS technology, and results are discussed.

This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record fT and fmax (>250 GHz)

For process monitoring and device modeling, a new method to determine the different components of the base resistance of bipolar transistors has been developed. Dual base test structures have been improved to extract the sheet resistance value of each of these components using dc measurements.This method is applied to a state-of-art double poly ST BiCMOS technology, and results are discussed.