Depuis l'apparition des premiers circuits MMICs (Monolithic Microwave Integrated Circuits ou circuit intégré monolithique hyperfréquence), en 1975, cette technologie n'a cessé d'évoluer et a maintenant de nombreuses applications. Cet article présente les performances, technologies et outils de conception de ces circuits. Puis il détaille plus particulièrement les procédés et étapes technologiques tant pour les filières III-V que Silicium.

This paper goes into SiGe BiCMOS technology requirements to serve LEO SATCOM User Terminals and Optical Interconnects. Technology characteristics and circuit results of platforms currently in production for these applications are presented. It also discusses prospects of low-noise and high-speed BiCMOS for both applications and technology roadmap, including the heterogeneous integration panorama.

We present 94 GHz large-signal load-pull measurements of a transferred InP/GaAsSb double heterojunction bipolar transistor fabricated on a high-resistivity silicon (Si-HR) substrate. The characterized device features an emitter area of 0.19 & times;8.9 mu m(2). Biased for highest power, an output power of 16.79 dBm was achieved corresponding to a power density of 28.32 mW/mu m(2) or 5.38 W/mm. Biased for maximum power-added-efficiency (PAE), a peak value of 26 % was obtained along with an output power of 12.17 dBm corresponding to a power density of 9.8 mW/mu m(2) or 1.86 W/mm. These results highlight the tremendous impact of a substantial reduction in thermal resistance and, consequently, illustrate the detrimental effects of device self-heating on RF power performance.

InP HBT technology is a suitable candidate for the future 6G networks that require very high bandwidth. It has already demonstrated high-frequency operation with $f_{\text {max }}$ exceeding 1 THz [1]. However, this performance comes at the cost of aggressive scaling which increases thermal resistance ($R_{t h}$) due to device narrowing and leads to self-heating limiting overall performance. Transferring InP DHBT to a high-thermal-conductivity substrate has shown a drastic reduction of $R_{t h}$ by $65 \%$ on Si-HR [2] and $75 \%$ on SiC [3] thanks to their superior heat dissipation properties however its effect on output power remains unexplored. We present continuous wave (CW) large-signal load-pull measurements at 94 GHz of a transferred InP/GaAsSb DHBT transistor fabricated on a high-resistivity silicon substrate (HR-Si). The characterized device features an emitter area of $0.29 \times 4.9 \mu \mathrm{~m}^{2}$ and was biased for both maximum output power and maximum power-added-efficiency (P.A.E). A peak output power of $14.25 \mathrm{dBm}\left(18,84 \mathrm{~mW} / \mu \mathrm{m}^{2}\right)$ was achieved. This result demonstrates the impact of thermal dissipation in reducing self-heating and enabling higher output power.

This paper presents RF measurements on Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) device up to 500 GHz within a 55-nm BiCMOS platform. Utilizing the advanced 16-terms errors calibration methods, we successfully address the challenges of high-frequency measurements on small-scale devices with the extraction of the authentic maximum oscillation frequency (fMAX) of 500 GHz of the present transistor. These results are pioneering, to the authors knowledge, it is the first time that RF measurement up to 500 GHz are shown on SiGe HBTs using 16 terms errors model and demonstrating an excellent continuity between frequency bands.

This paper presents an integration of a lateral Si/SiGe heterojunction bipolar transistor (LHBT) device on an advanced Fully-Depleted-Silicon-On-Insulator (FD-SOI) Complementary Metal-Oxide Semiconductor (CMOS) process flow accompanied by a Technology Computer Aided Design (TCAD) study. The analysis is based on physics principles, explaining the behavior of the LHBT device. Although the simulated device shows significantly high performance, especially for the maximum oscillation frequency (fMAX), there are serious challenges in achieving the same performance on silicon. These challenges in creating high-performance devices in FD-SOI are presented.

A low-cost high-responsivity design of Si/SiGe heterojunction bipolar phototransistor (HPT) built in an industrial 55 nm-BiCMOS technology is integrated in a cascode configuration with a bipolar transistor (HBT) to be used for microwave-photonic communication receivers. Performances of both the cascode pair and the single heterojunction bipolar phototransistor are compared. At high-frequency, the cascode circuit has better performances than the single HPT stage. At 850-nm wavelength, the pair can reach a low-frequency responsivity of 3.24 A/W and a bandwidth of 0.69 GHz when coupling losses are corrected.

This letter presents performances of Si/SiGe heterojunction bipolar phototransistors (HPT) used for microwave photonics communication receiver link around 850nm. SiGe phototransistors are designed in an industrial 55-nm SiGe BiCMOS from STMicroelectronics without any change in the layers technology process. Different horizontal geometries of HPTs and biasing techniques were evaluated. The static responsivity of a 20x20 mu m(2) optical window HPT reached 20.7 A/W at 900nm. This is the highest static responsivities reported for a fully-integrated Si/SiGe HPT with vertical illumination. A 1.6-GHz bandwidth for a 10.5-A/W static responsivity was achieved for a 5x5 mu m(2) optical window HPT using current bias.

This paper investigates the impact of 3D hybrid bonding (3D-HB) interconnections on the performance of passive components, including transmission lines, inductors, capacitors, and transformers, at mm-wave frequencies up to 220 GHz. Measurements of the 3D-HB transmission lines highlight very low single-transition losses ($<0.2 \text{dB}$ at 100 GHz). A comparison between 2D planar and 3D-HB integrated designs shows a negligible impact of the 3D-HB technology below 100 GHz. At higher frequencies, in particular for inductors, the self-resonant frequency is shifted about $\mathbf{1 0}$% lower for the 3D-HB structure than for the 2D design. Finally, measurements of a transformer based on two single-turn (one turn per bonding side) spirals demonstrate high inductive coupling up to 65 GHz. These results underline the interest of 3D-HB interconnections for compact, efficient RF designs, enabling seamless integration and reduced interconnect losses in mm-wave applications.

This article explores the impact of the substrate network on the high-frequency performance characteristics of silicon/silicon-germanium (Si/SiGe) heterojunction bipolar transistors (HBTs). The influence of the substrate network becomes particularly significant at frequencies above 100 GHz, necessitating advanced measurement and de-embedding techniques. In this study, we employ the advanced 16-term error calibration method to accurately extract the maximum oscillation frequency (f(MAX)) up to 500 GHz. This approach allows us to observe second-order effects, such as the impact of substrate network, for the first time. Our findings reveal that the substrate network has significant implications for the optimization of high-frequency Si/SiGe HBTs, especially on f(MAX). The study provides insights into substrate-related parasitic effects and proposes strategies to mitigate these effects.

A new low-cost BiCMOS Heterojunction Bipolar Phototransistor (HPT) is fabricated for the first time in an industrial BiCMOS technology from STMicroelectronics with a "no change in process" approach. The static responsivity as a function of the biasing is determined from measurements at 850 nm for various HPT designs. Devices with a static responsivity level up to 40 A/W at 2.5V collector-emitter voltage biasing can be achieved when the device operates near its breakdown voltage. In its active region, at V-CE = 1V, a static responsivity level up to 12.2 A/W was obtained selecting the appropriate base biasing.

The technology transfer of terahertz wireless communication from research laboratories to commercial applications is a global strategic achievement currently pursued to match the ever-increasing demand for high-speed communication. The use of commercial integrated electronics for the detection of THz waves is an intriguing challenge which has enticed great interest in the scientific research community. Rapid progress in this field has led to the exploitation of THz direct detection using standard CMOS technology based on the so-called self-mixing effect. Our research, stemming out of a collaboration between Sapienza University of Rome and STMicroelectronics company, is focused on the complete design process of a THz rectifier, realized using 50 nm ST B55 CMOS technology. In this paper, we report the optimization process of a case-study receiver, aimed to demonstrate the feasibility of direct demodulation of the transmitted OOK signal. A relatively limited bandwidth extension is considered since the device will be included in a system adopting a radiation source with a limited band. The design refers to a specific technology, the 60 nm MOS in B55X ST; nevertheless, the proposed optimization procedure can be applied in principle to any MOS device. Several aspects of the rectification process and of the receiver design are investigated by combining different numerical simulation methodologies. The direct representation of the rectification effect through the equivalent circuit of the detector is provided, which allows for the investigation of the detector–amplifier coupling, and the computation of output noise equivalent power. Numerical results are presented and used as the basis for the optimization of the receiver parameters.

Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) are used daily, mainly in the communication field. Their co-integration with Complementary Metal Oxide Semiconductor (CMOS) technology, i.e. BiCMOS, enables versatile microchips that combine analog, radio-frequency and digital functions. Applications that drive the development of BiCMOS technologies today are Low Earth Orbit (LEO) satellite communications, for which the minimum noise figure of SiGe HBT (NFMIN) between 10 and 30 GHz is one of the most critical figures of merit on the receiver side. It is expected that BiCMOS will play a significant role in the 6G infrastructure, in particular for communications in the D-band spectrum (110-170 GHz), for which the challenge at HBT level is to demonstrate maximum oscillation frequency fMAX > 500 GHz. Benefitting from mature CMOS technologies, the smallest CMOS node used in BiCMOS chips is the 45 nm partially depleted silicon on insulator [1]. STMicroelectronics has been using the 55 nm node since 2014 [2]. These nodes are today sufficient to address the digital content of the targeted circuits, while offering the right performance/cost trade-off. Although the HBT performance depends on lateral scaling too, it is mainly driven by the 1D dopant profile. Multiple Si and SiGe layers are grown by Reduced Pressure-Chemical Vapor Deposition (RP-CVD) epitaxy, defining the core of the device. For a self-aligned architecture such as STMicroelectronics’ EXBIC architecture, four epitaxy steps with different doping levels are required (Fig. 1) [3]. Improvement of key electrical parameters such as NFMIN and fMAX depends on the optimization of these epitaxies. Specifically, the collector epitaxy can be performed by non-selective or selective epitaxy, each with its advantages and drawbacks. Non-selective epitaxy is performed early in the BiCMOS process flow, with no thermal budget impact on the CMOS process. This kind of epitaxy is also cheaper but can cause auto-doping at the epitaxial interface [4] and put constraints on the collector integration, that are solved by the selective epitaxy of the collector. This scheme is used in the latest devices from both STMicroelectronics [3] and GlobalFoundries [5]. The transit time of electrons through the base is determined by its thickness and its composition. Significant performance gains have been achieved by switching from pure Si to a graded SiGe base architecture. The bandgap variation due to the graded SiGe composition creates a pseudo-electric field that accelerates the minority carriers transport through the base and limits electron-hole recombination. The addition of carbon into the base limits the boron diffusion and reduces the base thickness, further improving performance. However, only substitutional carbon atoms are required while interstitial carbon atoms must be avoided. The amount of carbon, incorporated in fully substitutional sites, is controlled by the silicon precursor used during RP-CVD epitaxy. At a given temperature it has been shown that a more reactive silicon precursor allows for better substitutional carbon incorporation. By switching from SiH2Cl2 (DCS) to SiH4, the amount of substitutional carbon atoms was increased by 250 % [6]. Following this idea, Si2H6 has been introduced as a silicon precursor to achieve even better substitutional carbon incorporation due to its higher reactivity [7]. The emitter process is usually performed by non-selective Si:As epitaxy. This type of epitaxy produces polycrystalline Si:As with a monocrystalline Si:As core above the crystalline base. The emitter resistance can be reduced by processing a fully monocrystalline emitter. A possible solution involving low temperature deposition and solid phase epitaxial regrowth is proposed [8]. An overview of the existing problems for each epitaxy step will be given, outlining potential solutions to increase HBT performance to meet customer requirements. [1] J. Pekarik et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 1-4 (2021) [2] P. Chevalier et al., IEEE International Electron Devices Meeting (IEDM),77-79 (2014) [3] A. Gauthier et al., IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 187-190 (2023). [4] P. Jerier and D. Dutartre, J. Electrochem. Soc. 146 ,331 (1999) [5] J. Pekarik et al., ECS Transactions, 109, 141 (2022) [6] F. Brossard et al., International SiGe Technology and Device Meeting (ISTDM), 1-2 (2006) [7] J. Vives et al., ECS Transactions, 109 (4), 237-248 (2022) [8] F. Deprat et al., ECS Transactions, 109, 159 (2022) Figure 1

This paper presents a study of the influence of direct hybrid bonding interconnections on a grounded coplanar waveguide in a 3D integration technology at mm-wave frequencies up to 120 GHz. The considered transmission line is implemented in B55X (Bi)CMOS technology from STMicroelectronics with five metal layers. The investigation explores the impact of the top die hybrid bonding interconnection for 3D integration, the presence of hybrid bonding metallization pads, and variations in their location. The performance metrics, specifically attenuation loss and relative permittivity, were evaluated, revealing that the HB interconnection results in very low loss and minimal impact. When assessing the hybrid bonding and metallization dummies without the top die, only slight effects were observed. However, when both the hybrid bonding metallization and top die are considered, slightly higher losses and an increase in permittivity due to the top die were noted. Finally, a study illustrating the impact of the spatial positioning of hybrid bonding metallization above the grounded coplanar waveguide validates the robustness of the design with 3D hybrid bonding metallization pads.

This paper presents how the BiCMOS055X technology from STMicroelectronics is defined to serve wired, wireless, and satcom applications with a versatile competitive offer. Technology content is described and differences with the previous generation are highlighted. Performances of all the devices (active and passive) are reviewed, including the SiGe HBT reliability. The design platform offers, and related qualification strategy are also discussed.

The performance of an HBT is primarily influenced by 1D dopant profile obtained by CVD epitaxy. Typically, three epitaxial layers are required to construct an HBT: the collector, the intrinsic base, and the emitter. Collector layer can be grown by either NSEG or selective epitaxy. While the NSEG process is cost effective, it results in autodoping. Switching to selective epitaxy can mitigate autodoping but must be controlled to minimize faceting. The intrinsic base is critical to device performance, with boron positioning being a key factor. Incorporating substitutional carbon atoms into the SiGe lattice significantly reduces boron diffusion. By switching from SiH4 to Si2H6, three times more substitutional carbon incorporation in SiGe without interstitial C atoms at 550 °C is achieved. Below 600 °C, the co-flow approach is ineffective, necessitating a cyclic deposition-etch (CDE) approach to maintain selectivity. Comparisons between CDE and single deposition-etch (DE) approaches show that CDE degrades the monocrystalline SiGeC:B layer, resulting in high RMS roughness and degraded morphology. In contrast, the DE approach shows promising results with lower RMS roughness and no significant morphological degradation. The last epitaxial layer discussed is the emitter. Current fabrication methods involve non-selective Si:As deposition at growth temperatures above 600 °C, resulting in polycrystalline Si:As deposition on dielectrics and monocrystalline Si:As growth on silicon. A novel process developed at 550 °C using Si2H6 as silicon precursor yields monocrystalline emitter by amorphous deposition on dielectrics followed by solid phase epitaxial regrowth. However, this process exhibits TED of arsenic, making it currently not viable.

The linearity and efficiency of two distinct SiGe HBT devices, manufactured using different process technologies (B55 & B55X intermediate) by STMicroelectronics, are examined with a focus on energy-efficient applications under large-signal conditions.

Silicon germanium (SiGe) BiCMOS technology, often simply called SiGe, is used for high-performance SiGe heterojunction bipolar transistors (HBTs, versus Si bipolar junction transistors) and high-quality passive devices on a CMOS platform (see Figure 1 [1]). This combination offers better performance at lower cost than CMOS and III-V technologies and is able to address most demanding analog and RF applications, while benefiting from the advantages of SiGe HBTs and CMOS for digital functions [2].