This paper presents how the BiCMOS055X technology from STMicroelectronics is defined to serve wired, wireless, and satcom applications with a versatile competitive offer. Technology content is described and differences with the previous generation are highlighted. Performances of all the devices (active and passive) are reviewed, including the SiGe HBT reliability. The design platform offers, and related qualification strategy are also discussed.

This paper discusses technological choices and resulting performances of an innovative Si/SiGe HBT architecture developed for a new 55-nm BiCMOS platform from STMicroelectronics targeting LEO satellites user terminals application in Ku-Ka bands. Transistor architecture has been designed to combine a low-noise performance with a cost-effective technology (for high-volume production), that are two major requirements for LEO satellite user terminals. Collector integration is widely simplified compared to previous BiCMOS technologies developed by STMicroelectronics taking advantage of ion implantation capabilities. Low-noise performance is addressed by a new generation of emitter-base architecture featuring an epitaxial base link, reducing the base resistance. Record noise performances are demonstrated with $NF_{\text{MIN}}\sim$ 0.6-dB at 20 GHz at device level and 1.13-dB at 11.85 GHz at circuit (packaged receiver) level associated to a gain of ~28dB. SiGe HBT also features −390 GHZ $f_\mathrm{T}$ and −500-GHz $f_\text{MAX}$

RF Front End Modules (FEMs) are currently achieved using CMOS Silicon-on-insulator (SOI) as the dominant technology for RF switches integration in handsets RF FEMs [1]. But for cost sensitive market requiring less stringent performances (such as WiFi), high resistivity (HR) bulk SiGe BiCMOS technology has been proposed to achieve RF FEM System on Chip (SOC) integration [2], [3]. In this paper, we review the optimization of an advanced 200-mm HR SiGe BiCMOS technology based on a previous 0.13-μm process [4]. State of the art performances have been achieved from RF switch point of view with R ON × C OFF of 169 fs and WiFi SPDT RF switch exhibiting insertion loss of ~0.8 dB @ 5.5 GHz and power handling capability exceeding 31 dBm.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

This paper presents different de-embedding methods applied in semiconductor industry, used to retrieve intrinsic device performances from high frequency S-parameters On-wafer measurement. A de-embedding method with a reduced set of dummies is proposed for conducting accurate on-wafer device measurement in the gigahertz range. The experimental results on a device characteristic up to 110GHz show that it has a comparable accuracy than a more complex one.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 μm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz fT and 370 GHz fMAX associated with a CML ring oscillator gate delay τD of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

The accurate determination of the emitter series resistance R E has been topic for numerous investigations throughout the development of modern bipolar device technologies. A good knowledge of the parasitic resistances of the device under test is important due to the apparent voltage drops over these resistors in high current operation. Opposed to the base and collector resistance today there are no appropriate individual test structures that allow for a precise determination of the emitter resistance. In this work we present the application of a new extraction method to a recent SiGeC HBT device technology for mmW applications. The new method allows a precise parameter determination of the desired resistance values without adding additional cost for a dedicated test structure.

Stress investigations have been carried out on SiGe HBTs from STMicroelectronics BiCMOS9MW technology. The strain created by the stack of metal connections impacts the base bandgap of the transistors: from the reference to the denser dummies structure, a 9.1 meV bandgap energy variation is pointed out. Dummies structures were embedded for both DC and HF characterizations which showed a 25% increase for the collector current, and a 21% and 12% increase for the transit frequencies fT and fMAX respectively.

The parasitic collector resistance is of high importance for device performance of HBT manufactured in advanced SiGe technologies. The external collector resistance contribution RCx is a critical modeling parameter for AC and transient operation. If the collector resistance is estimated incorrectly, the RF performance of the modeled device may significantly differ from the manufactured HBT. An advanced test structure for resistance extraction is presented and measured in two different ways. The obtained resistance values and extraction results are verified using analytical equations and quasi-three-dimensional device simulations.

The internal base resistance, that presents a crucial figure of merit and parameter for accurate RF device modelling is investigated. The reliability of a widely used approach for geometry scalable parameter extraction is analysed using measurement data of a state-of-the-art SiGeC HBT technology. The obtained results are used for numerical device simulations of the inner base as well as the base link region to verify the resistance values. Furthermore results from an alternative approach using measured S-parameter data from standard RF structures are compared by means of the semi-circle method.

In device modelling and simulation the base resistance is a crucial parameter for RF characteristics such as the maximum frequency of oscillation (fmax) and noise figure (NFmin). The robustness and reliability of a well-established extraction procedure is analysed using measurement data from a state-of-the-art SiGeC HBT technology. The influence of variation of key technology parameters on the extraction flow and extracted parameters is evaluated using data from a process split. The sheet resistances obtained from the measured date are used in a simulation trial. The suitability and robustness of the method is further evaluated using synthetic data from numerical device simulation with one-dimensional test structures.

This paper presents an overview of RF calibration and pad de-embedding techniques, discusses limitations and demonstrates methods for accuracy improvement applicable for the characterization of advanced BiCMOS HBTs. The impact of the reference plane location is discussed. Numerous experiments with different device geometries showed that the in-situ (on-wafer) calibration yields the most accurate results. For a probe-tip calibration, a multiple-dummy de-embedding is crucial to improve measurement accuracy. A comparison with the compact model (HICUM V2.30) confirmed the findings.

The base-emitter (BE) depletion charge weighting factor hjei accounts for the variation of the BE space charge region (SCR) with bias. In former HICUM model releases this weighting factor was a fixed model parameter value independent of device bias or temperature. With recent technology advancements and aggressively scaled vertical profiles incorporating significant germanium fractions a new model formulation was introduced. However the increased model complexity calls for a more sophisticated parameter extraction strategy. A novel extraction method is presented that is based on the solution of the new HICUM L2.30 formulation with the help of the Lambert W function. The extraction flow is presented and validated using a mature BiCMOS process technology available for mass-production.

This paper summarizes the technological developments carried out in STMicroelectronics to raise the fT / fMAX of SiGe HBTs up to ~ 300 GHz / 400 GHz. The noise and power performance in the W-band of different SiGe HBT generations are compared along with CML ring oscillators and circuit results up to the D band.

High frequency noise parameters (NF min , R n , B opt and G opt ) determination of Si/SiGe HBTs from STMicroelectronics B5T technology are provided for the first time in the millimeter-wave range. In this paper, an integrated tuner is used for the extraction of high frequencies noise parameters with the multi-impedance method. The designed tuner is composed an active part with a low noise amplifier (LNA) and a passive part with a high performances travelling wave digitally tunable capacitance (DTC), both in series with a transmission line design for phase shifting. Measurements exhibit a state of the art NF min lower than 2 dB at 68 GHz for the HBT.

This work presents design methodology of on-wafer calibration standards covering frequencies up to 110 GHz and optimized for the BiCMOS processes. We discuss such topics as layout optimization of distributed and lumped standards, measurement and verification of electrical characteristics along with the definition of the on-wafer calibration reference impedance and measurement reference plane. Also, we present calibration verification results and some characteristics of an active DUT implemented in Si/SiGe:C ST Microelectronics' BiCMOS9MW process technology.

This paper presents investigation results of the probe-tip calibration impact on the BiCMOS HBT small-signal parameter measurement accuracy. Popular calibration procedures were applied on the same data set and followed by the two-step de-embedding from the device dedicated Compete-Open and Complete-Short dummy elements. Experimental results showed that the observed difference in cold HBT parameters and parameters of passive devices was minimized by the de-embedding step. The f(T) and f(MAX) demonstrated higher sensitivity to the probe-tip calibration residual errors.

This paper presents extraction methodologies for advanced SiGe heterojunction bipolar transistors (HBTs). Demonstrated methods focus on extracting the transfer current related parameters over a large temperature range for the new version 2.3 of the compact HBT model HICUM Level 2. Also shown are the limitations of existing extraction methods. Results for DC and AC characteristics are shown for different temperatures.

On-wafer RF calibration methods are compared to the conventional Impedance Standard Substrate (ISS) calibration combined with a dummies de-embedding approach for transistors of an advanced BiCMOS process. We discuss the design of customized calibration standards addressing specifics of the silicon BiCMOS process. Our results show that on-wafer calibration methods are the most suitable approaches for accurate characterization of sub-THz SiGe HBT's.