High-resolution transmission electron microscopy and scanning tunneling microscopy have been combined to examine the structure of the thin "native" oxide that forms on silicon surfaces at room temperature. Differences in the cleaning procedures for silicon wafers may affect the morphology of this oxide and critically influence further processing on the silicon substrates. An etch that ended with a dip in hydrofluoric acid provided a thinner oxide and a lower interface step density than did a sulfuric peroxide treatment. The availability of complementary information from high-resolution transmission electron microscopy and scanning tunneling microscopy is discussed.

The authors have investigated the combined effect of the addition of TCA (trichloroethane) and an intermediate annealing step to reduce the density of defects that develop in thin oxides during the oxidation process. Thin oxides (85-95 AA) were grown at 950 degrees C in dry O2 with varying amounts of Ar dilution and with or without TCA. Oxide breakdown voltage, current against voltage (Fowler-Nordheim parameters) and both high-frequency and quasi-static capacitance against voltage measurements were used to characterise the electrical properties of thin oxides. They show that the addition of TCA is most effective in improving the electrical properties of thin oxides when combined with an intermediate annealing step.

Thin oxides (≃80 Å) have widespread application as the tunnel oxides for floating gate EEPROM devices and as gate dielectrics for submicron MOS devices. Many EEPROM memory cells require a window to be etched by plasma etching into a relatively thick layer of prior to tunnel oxide growth. The high accuracy of defining the tunnel gate area requires sophisticated definition techniques such as stepper lithography and anisotropic plasma etching. This paper describes the effects of anisotropic plasma etching of a 900Å thick thermal oxide on the properties of thin oxides grown subsequently. It is shown that the thin oxide growth rate as well as the oxide breakdown voltage characteristics is affected by the plasma etching conditions.

We have developed a technique for growth of thin oxides (80–90Å) with an intermediate annealing step. The oxides exhibit a tight distribution in breakdown voltage measurements leading to defect density less than 5/cm2, intrinsic breakdown field of 12 MV/cm, and a value of less than for interface trap density in midgap. The inferior electrical properties of thin oxides grown by conventional methods in dry oxygen with Ar dilution have been correlated with interface roughness using high resolution transmission electron microscopy. The intermediate annealing process may be used to improve the endurance and retention properties of EEPROM devices and alleviate the degradation of thin oxides in short‐channel MOS devices.

AbstractMit dem Ziel einer Eigenschaftsverbesserung von Halbleiterbauteilen wird gezeigt, daß für das Aufwachsen dünner Oxidschichten (80‐90 Å) auf Si eine Zstufige Oxidation mit dazwischengeschaltetem Tempern bei 1050°C günstiger ist als Tempern nach vollendetem Oxidwachstum.