Coarse-Grained Reconfigurable Arrays (CGRAs) are a promising class of architectures for accelerating applications using a large number of parallel execution units for high throughput. While the model allows for tools that can automatically parallelize a single task across many processing elements, all processing elements are required to perform in lock step. This makes applications that involve multiple data streams, multiple tasks, or unpredictable schedules more difficult to program and inefficient in their use of resources. These applications can often be decomposed into a set of communicating kernels, operating independently to achieve the overall computation. Although competing accelerator architectures like Massively Parallel Processor Arrays (MPPAs) can make use of this communicating processes model, it generally requires the designer to decompose the design into as many kernels as there are processors to be used. While this is excellent for executing unrelated tasks simultaneously, the amount of resources easily utilized for a single task is limited. We are developing a new CGRA architecture that enables execution of multiple kernels of computation simultaneously. This greatly extends the domain of applications that can be accelerated with CGRAs. This new architecture poses two problems that we describe in this paper. First, the tools must handle the decomposition, scheduling placement and routing of multiple kernels. Second, the CGRA must include new resources for coordinating and synchronizing the operation of multiple kernels. This paper is a digest of the project’s previously published results [17,18,19,20,21].

Bioinformatics is an emerging field with seemingly limitless possibilities for advances in numerous areas of research and applications. We propose a scalable FPGA-based solution to the short read mapping problem in DNA sequencing, which greatly accelerates the task of aligning short length reads to a known reference genome. We compare the runtime, power consumption, and sensitivity of the hardware system to the BFAST and Bowtie software tools. The hardware system demonstrates a 250X speedup versus BFAST and a 31X speedup versus Bowtie on eight CPU cores. Also, the hardware system is more sensitive than Bowtie, which aligns approximately 80% of the short reads, as compared to 91% aligned by the hardware.

Pipelining and retiming are two related techniques for improving the performance of synchronous circuits by reducing the clock period. Unfortunately these techniques are unable to improve many circuits encountered in practice because the clock cycle is limited by a critical cycle which neither technique can change. We present in this paper a new optimization technique that we call architectural retiming which is able to improve the performance of circuits for which both pipelining and retiming fail. Architectural retiming achieves this by increasing the number of registers on the critical cycle while preserving the functionality and perceived latency of the circuit. We have used the name architectural retiming because it both reschedules operations in time and modifies the structure of the circuit to preserve its functionality. This concept generalizes several ad hoc techniques such as precomputation and branch prediction that have been applied to synchronous circuits. We first describe the basic ideas behind architectural retiming and then give two examples of applying it to real circuits. Finally, we outline some of the issues that must be addressed to automate the architectural retiming process.

Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. We show that a modest amount of specialization reduces the area-delay-energy product of an optimized architecture to 0.86× a baseline architecture. Furthermore, we provide a design guideline that allows an architect to customize the contents of the computing fabric just by examining the profile of benchmarks within the application domains.

Crunching large graphs is the basis of many emerging applications, such as social network analysis and bioinformatics. Graph analytics algorithms exhibit little locality and therefore present significant performance challenges. Hardware multithreading systems (e.g., Cray XMT) show that with enough concurrency, we can tolerate long latencies. Unfortunately, this solution is not available with commodity parts. Our goal is to develop a latency-tolerant system built out of commodity parts and mostly in software. The proposed system includes a runtime that supports a large number of lightweight contexts, full-bit synchronization and a memory manager that provides a high-latency but high-bandwidth global shared memory. This paper lays out the vision for our system and justifies its feasibility with a performance analysis of the run-time for latency tolerance.

It is clear that Exascale computing will require alternative computing substrates such as FPGAs as an adjunct to traditional processors to stay within power consumption constraints. Executing applications, or parts of applications, using specialized, fine-grained computing structures configured into FPGAs can achieve a large increase in both performance and energy-efficiency for many important applications. Unfortunately, the process of designing and implementing these specialized hardware structures is tedious and requires expertise in hardware design. The lack of programming models and associated compilers for configurable computing has impeded progress in the use of FPGAs in large-scale computing platforms. This paper describes a parallel programming model and compilation strategy that we are exploring as a way to describe large-scale applications using familiar concepts and abstractions, but which can be implemented using large-scale, fine-grained parallel computing structures. We first outline this model and show how it can be used to develop a scalable parallel solution for the genomic shortread reassembly problem.

We believe that FPGA-like parallel coprocessor accelerators can be programmed efficiently at the “C level” of abstraction. In order to support this claim we define an abstract architectural model of accelerators that conveys the kind of high-level behavior and performance characteristics that the von Neumann model conveys to programmers of conventional processors. Using the model as a guide we define a programming language and compilation strategy that: 1. do not impose programming style restrictions that are not inherent in the model, 2. do not introduce serious inefficiencies, and 3. are performance portable across implementations of the model. In this dissertation I describe C-level programming of accelerators broadly, and make three particular contributions to the programmability of accelerators. Enhanced loop flattening is a new method for translating loop nests with arbitrary static control flow into a form that can be efficiently pipelined with conventional algorithms designed for simple loops. This method advances the goal of supporting a wide set of programming styles with reasonable efficiency. Parallel accelerators have statically managed resources—like local memories—that vary widely in capacity from one implementation to the next. In order to get close to peak performance, applications must be tuned to the specific resources available in a given implementation, and empirical auto-tuning is an attractive way to do that. I propose and evaluate a new probabilistic auto-tuning method that elegantly handles situation where many possible configurations of the application fail to work at all because they exceed some architectural resource limit. For many applications, achieving good performance on parallel accelerators requires deep loop pipelining, which requires dramatically reordering the individual operations in the application. Local dependencies between operations can be respected by compilers relatively easily, but non-local dependencies force implementations to choose between conservatively not reordering operations (which might kill performance), proving that reordering preserves the meaning of the program (which is impossible in the general case), or making unsound transformations (which programmers generally dislike). I propose a mostly sequential operational semantics for C-level streaming languages targeted at parallel accelerators that offers enough flexibility to the implementation to achieve good performance, deviates from conventional program-order semantics in fairly modest and understandable ways, and provides tools with which the programmer can control the reordering performed by the implementation. These innovations are evaluated in the context of Macah, a new C-like language developed in the Mosaic group at the University of Washington. For validation we use a number of compute-intensive benchmarks developed by members of the Mosaic group and other contributors.

Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rely heavily on centralized storage, e.g. register files and embedded memories, spatial processors require many small storage structures to efficiently manage values that are distributed throughout the processor's fabric. The goal of this work is to determine the advantages and disadvantages of different architectural structures for storing values on-chip when optimizing for energy efficiency as well as area. Examination of applications for coarse-grained reconfigurable arrays (CGRAs) shows that most values are short-lived; they are produced and consumed quickly, but the distribution of value lifetimes has a reasonably long tail. We take advantage of this distribution to optimize register storage structures for managing short-, medium-, and long-lived values. We show that using a combination of register storage structures, each tailored for values with different lifetimes, provides a reduction in overall area-energy product to 0.69x the area-energy of the baseline architecture, without loss of performance. Finally we provide energy profiles, characteristics, and comparisons of each register structure to enable architects to guide future design choices.

Spatially-tiled architectures, such as coarse-grained reconfigurable arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, embedded, and scientific computing domains. In contrast to field-programmable gate arrays (FPGAs), another common accelerator, they typically time-multiplex their processing elements and are word rather than bit-oriented. These differences lead us to re-examine some of the traditional architecture choices made for FPGAs as we move to these coarser-granularity architectures. In this paper we study the efficiency of time-multiplexing global interconnect as architectures scale from single-bit to multi-bit datapaths. Using the Mosaic infrastructure, we analyzed the design trade-offs involved in static vs. time-multiplexed routing for global interconnect channels, as well as the benefit of including a dedicated bit-wide control interconnect to supplement the word-wide datapath of a CGRA. We show that a time-multiplexed interconnect is beneficial in these coarse-grained systems, reducing the area-energy product to 0.32times the area-energy product of a fully static interconnect. We also show that for our benchmarks, which include single-bit control logic, providing both word and bit-wide interconnect resources further reduces the area-energy product to 0.94times that of an exclusively word-wide interconnect.

In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that provides feedback from the placer to the scheduler to meet the constraints of a fixed frequency device with configurable interconnect. Using a new dynamic clustering method during placement, we achieved a 1.3x improvement in throughput of mapped designs. Finally, we introduce an enhancement to the PathFinder algorithm for targeting architectures with a mix of dynamically multiplexed and statically configurable interconnects. The enhanced algorithm is able to successfully share statically configured interconnect in a time-multiplexed way, achieving an average channel width reduction of .5x compared to non-shared static interconnect.

Coprocessor accelerator architectures like FPGAs and GPUs are increasingly used in embedded systems because of their high per- formance on computation-heavy inner loops of a variety of appli- cations. However, current languages and compilers for these archi- tectures make it challenging to efficiently implement kernels that have complex, input-dependent control flow and data access pat- terns. In this paper we argue that providing language support for such kernels significantly broadens the applicability of accelerator architectures. We then describe a new language-called Macah-and compiler that provide this support. Macah is a "C-level" language, in the sense that it forces programmers to think about some of the abstract architectural characteristics that make accelerators different from conventional processors. However, the compiler still fills in several important architecture-specific details, so that programming in Macah is substantially easier than using hardware description languages or coprocessor-specific assembly languages. We have implemented a prototype Macah compiler that produces simulatable Verilog which represents the input program mapped onto a model of an acceler- ator. Among other applications, we have programmed a complex kernel taken from video compression in Macah and have it running in simulation.

Field-programmable gate arrays (FPGAs) have recently become a dominant implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych1, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm which handles the routeability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm which can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications.

Coarse-grained reconfigurable architectures (CGRAs) have the potential to offer performance approaching an ASIC with the flexibility, within an application domain, similar to a digital signal processor. In the past, coarsegrained reconfigurable architectures have been encumbered by challenging programming models that are either too far removed from the hardware to offer reasonable performance or bury the programmer in the minutiae of hardware specification. Additionally, the ratio of performance to power hasn’t been compelling enough to overcome the hurdles of the programming model to drive adoption. The goal of our research is to improve the power efficiency of a CGRA at an architectural level, with respect to a traditional island-style FPGA. Additionally, we are continuing previous research into a unified mapping tool that simplifies the scheduling, placement, and routing of an application onto a CGRA.

All modern hardware design makes use of hardware description languages like Verilog and VHDL. Thus these languages are presented very early in the curriculum, often in the first design course. Unfortunately, these languages often cause substantial confusion for students learning hardware design, particularly students that have experience writing programs in sequential languages like C and Java. To address this problem, we have defined a language called Abstract Verilog which is similar to Verilog, but which has well-defined, clean parallel execution semantics. Abstract Verilog has a somewhat restricted syntax in order to reduce the cognitive load for new students. However, almost any program that can be written in Verilog can be written in Abstract Verilog, where it is shorter and easier to understand. We have used Abstract Verilog successfully in both introductory and advanced design classes.

Platform FPGAs that integrate sequential processors with a spatial fabric have become prevalent. While these hybrid architectures ease the burden of integrating sequential and spatial code in a single application, programming them, and particularly their spatial fabrics remains challenging. The difficulty arises in part from the lack of an agreed upon computational model and family of programming languages. In addition, moving algorithms into hardware is an arcane art far removed from the experience of most programmers. To address this challenge, we present a new type architecture, an abstract model analogous to the von Neumann machine for sequential computers, that can serve as common ground for algorithm designers, language designers, and hardware architects. We show that many parallel architectures, including platform FPGAs, are implementations of this type architecture. Using examples from a variety of application domains, we show how algorithms can be analyzed to estimate their performance on implementations of this type architecture. This analysis is done without having to delve into the details of any architecture in particular. Finally, we describe some of the common features of languages designed for expressing micro-parallelism, highlighting connections with the type architecture

For some time now, configurable computing has been hailed as the future for application-specific architectures. The purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, and implementations can be fixed or upgraded in the field. But in spite of many attempts to move configurable computing platforms into the mainstream, they have yet to achieve their full promise. This talk will explore the barriers that have kept configurable computing on the sidelines thus far, and suggest steps that we might take to take advantage of its full potential

Field-programmable gate arrays are frequently used to implement system interfaces and glue logic. However, there has been little attention given to the special problems of these types of circuits in FPGA architectures. In this paper we describe Montage, a Triptych-based FPGA designed for implementing asynchronous logic and interfacing separately-clocked synchronous circuits. Asynchronous circuits have different requirements than synchronous circuits, which make standard FPGAs unusable for asynchronous applications. At the same time, many asynchronous design methodologies allow components with greatly different performance to be substituted for one another, making a design environment which migrates between FPGA, MPGA, and semi-custom implementations very attractive. Similar problems also exist for interfacing separately-clocked synchronous circuits. We discuss these problems, and demonstrate how the Montage FPGA satisfies the demands of these classes of circuits.

Configurable computing has captured the imagination of many architects who want the performance of application-specific hardware combined with the reprogrammability of general-purpose computers. Unfortunately, onfigurable computing has had rather limited success largely because the FPGAs on which they are built are more suited to implementing »ndom logic than computing tasks. This paper presents RaPiD, a new coarse-grained FPGA architecture that is optimized for highly repetitive, computation-intensive tasks. Very deep application-specific computation pipelines can be configured in RaPiD. These pipelines make much more efficient use of silicon than traditional FPGAs and also yield much higher performance for a wide range of applications.

The use of Application Specific Integrated Circuits (ASICs) for processing Internet Protocol (IP) packets is becoming infeasible due to increasing network wire transmission speeds, coupled with frequent improvements to existing algorithms. Development time and cost to fabricate a new generation of ASICs to implement newly developed algorithms is increasing. The age of programmable network processors (NPs) has arrived, since their flexibility allows reuse and thus amortizes their development cost over successive generations of network applications. The flexibility of network processors comes at a price; there is a trade-off in performance compared to ASICs. One major factor is the performance of the memory subsystem. This dissertation discusses the design of memory hierarchies for network processors to achieve high performance in IP packet forwarding and classification. We demonstrate how caching can be used to improve the performance of a trie-based IP forwarding algorithm. We develop a new packet classification algorithm based on partitioning classification rules into separate categories. Packets are classified independently using each rule category and then results are combined. The advantage is two-fold: parallel computation and reduced memory requirements per rule category. The algorithm is thus well-suited for implementation on multiple NPs which have limited memory. We justify our approach through trace-driven simulation.