Traditional FPGAs suffer from long reconfiguration latencies, ranging from milliseconds to seconds, which significantly limits their usage in applications that require rapid multi-context switching and dynamic partial reconfiguration. To overcome this barrier, we propose vertical FPGA (vFPGA), a novel 3D FPGA and packaging co-design methodology that leverages advanced packaging to achieve sub-mu s full-chip reconfiguration, while maximizing the on-chip storage capacity for multiple configuration contexts. In vFPGA, we partition a 2D FPGA die into two dies: a bottom die with the conventional programmable fabric, and a top die with memory banks and control logic to store multiple configuration contexts. These two dies are interconnected face-to-face through high density, vertical connections, such as micro bumps, Cu pillars, or hybrid bonding, which enable high-throughput, parallel programming paths that rapidly reconfigure the bottom die. Using the OpenFPGA framework with GlobalFoundries (GF) 22nm FDSOI process technology, we design both dies and conduct a comprehensive design space exploration (DSE) in light of packaging technology scaling. Our DSE focuses on the co-design of the pitch and dimensions of vertical interconnects, logic fabric partitioning, scan-chain partitioning, and memory bank selection and layout, with the objective of minimizing reconfiguration latency. In the physical implementation of 3D die-to-die integration, we also address critical signal integrity issues including clock synchronization and electrostatic discharge (ESD), along with power delivery challenges. Our simulation results demonstrate that, with 22nm dies and 45 mu m Cu pillar pitch, our new 3D FPGA achieves a sub-mu s reconfiguration latency, independent of the FPGA die size, yielding a 1,000x faster reconfiguration over traditional 2D FPGAs. Moreover, with hybrid bonding as vertical interconnects, we achieve sub-10 ns reconfiguration latency.
This paper presents Gatling-V1, an FPGA-optimized implementation of the RISC-V Vector extension that concurrently executes up to four vector instructions. The main innovation is using a multi-banked ASIC approach to build a vector register file from simple dual-port (1R1W) BRAMs rather than using traditional FPGA-based multi-port techniques. This saves both logic and BRAM, improves clock speed, and supports multiple overlapping in-flight instructions as well as vector chaining. However, it is limited to launching one vector instruction every two cycles. Using this technique, we build a RISC-V vector core that runs at 500MHz on AMD UltraScale+ HBM (16nm) with a 4R4W/8R8W register file and 2/4 fully parallel ALUs that use chaining (convoying) to reach peak utilization on sequentially dependent (independent) instructions with vectors longer than 36/72 (4/8) elements of 64b words, respectively. On microbenchmarks, the 4-ALU implementation is over 6 times faster than Saturn-V, an FPGA-optimized RISC-V vector engine, while consuming only twice as many LUTs but similar BRAMs and DSPs.
Large-scale multi-FPGA systems are widely used in modern emulation systems. As a critical part of the multi-FPGA system design flow, TDM signal grouping and package pin assignment directly impact the final placement and routing in the FPGA physical implementation. Poor pin assignments cause severe congestion and timing degradation at the logic-element level, while existing approaches lack accurate congestion modeling during system-level partitioning. This paper presents Chimew, a novel pin assignment methodology that leverages placement prototyping to predict logic-element-level congestion before physical implementation precisely. The proposed method co-optimizes signal grouping and pin placement through iterative refinement guided by congestion-aware cost functions derived from fast global placement. Experimental results demonstrate a 28% congestion reduction and up to 2.87ns less worst negative slack (WNS) compared to industrial tools while achieving a 100% success rate across diverse multi-FPGA benchmarks.
Open vSwitch (OVS) is a key component in cloud and data center networks, yet its MegaFlow classifier imposes significant CPU overhead. Existing SmartNIC-based acceleration approaches for the MegaFlow classifier typically employ simplistic hardware offloading techniques, which exhibit limited scalability for dynamic, large-scale flow tables. Motivated by these challenges, we argue that a hardware accelerator specifically tailored for the MegaFlow classifier is necessary, forming the basis of our FPGA-based solution, MegaTurbo. The core innovations of MegaTurbo are threefold: (1) a scalable and hardware-friendly decision-tree based packet classification algorithm, specifically optimized for the structure of MegaFlow rules; (2) a novel hardware architecture incorporating multiple pipelined matching engines, designed to process multiple decision trees generated by the software algorithm in parallel; and (3) a heterogeneous framework composed of CPU and FPGA, which can work together to support online rule updates, with little and bounded impact on rule searching. Experimental results on a Xilinx Virtex UltraScale+ FPGA demonstrate that MegaTurbo achieves a sustained classification throughput of 500 MPPS while supporting dynamic rule updates at 300-500 KUPS on 100K-scale rulesets. These results not only validate the effectiveness of our domain-specific co-design approach, but also highlight the potential of FPGA-based SmartNICs to address the performance bottlenecks of software switches in large-scale cloud and data center networks.
VeriFire is a cloud-native, FPGA-accelerated framework which uses a new methodology for pre-silicon hardware verification. At its core, VeriFire provides a synthesizable RISC-V based IP that can be customized to interface with a wide spectrum of design types. This spectrum ranges from simple modules, such as floating-point unit, to medium-scale components, such as streaming data engines, and extends to complex systems including accelerators, memory hierarchies, and chiplet-based architectures. Each of these design types present a unique verification challenge. VeriFire addresses the demands of resource-intensive verification across diverse design methodologies. It delivers substantial speedups, provides high design visibility, a seamless transition from simulation to emulation, and reduced verification cost and time. Most importantly, it facilitates hardware/software co-design.
Circuits generated by dynamically scheduled high-level synthesis (HLS) outperform static counterparts when execution-dependent operation reordering is possible. A key opportunity are potential memory dependencies that static analysis cannot rule out: Statically scheduled circuits must assume a worst-case scenario, enforcing conservative in-order execution even when unnecessary. In contrast, dynamically scheduled circuits use load-store queues (LSQs) to detect access collisions at runtime and reorder accesses whenever possible. While effective, LSQs are costly in both area and timing due to their size and critical path. We argue that LSQs in application-specific circuits are overly generic, checking all ordering relationships instead of only the necessary ones. Instead of relying on LSQs, our approach generates dataflow circuits that enforce only essential dependencies, reducing resource usage while preserving execution time. We implemented our methodology in an open-source, state-of-the-art dynamic HLS compiler and compared it against optimized LSQs. Our solution exploits the same reordering opportunities to achieve consistently Pareto-optimal solutions in terms of wall-clock time and resources. On average, we obtain similar execution times (2% better) while reducing resources by 37%, offering a superior alternative for high-performance dataflow circuit synthesis.
As Moore's law slows down, developers face difficult choices between low-level HDLs (Verilog, VHDL) offering fine-grained control and higher-level tools (HLS and Chisel) promising improved productivity. While high-level tools accelerate development, performance gaps persist compared to expert HDL implementations. Prior studies emphasize end-to-end performance, offering limited insight into why tools excel or where performance diverges in the design hierarchy. We introduce a hierarchical framework for comparing hardware generation tools [1] by decomposing HPC kernels (FFT, GEMM, QR factorization) into reusable primitives (MAC arrays, butterflies, permutations, reduction trees). Across Verilog, Chisel, and Vivado HLS, we built an automated tool flow and synthesized similar to 1,500 variants on AMD Alveo U250, measuring resource utilization and frequency. We derived theoretical bounds for validation. Verilog achieves the highest frequency and lowest resource usage; Chisel performs comparably (5-15% gap), while HLS shows a 20-40% gap. All tools operate within bounds forwell-structured designs. Crucially, performance divergence arises during primitive assembly, indicating that high-level tools require better composition optimization. This reproducible framework provides actionable insights and is extensible to other tools, domains, and FPGA architectures.
Fully Homomorphic Encryption (FHE) enables privacy-preserving computation on encrypted data. However, it incurs massive computation and DRAM traffic overheads, making hardware acceleration essential. Existing FPGA-based solutions offer limited exploration of bandwidth utilization and memory optimizations, leaving room for further performance improvements. In this paper, we present HERA, a bandwidth-efficient accelerator for FHE on High Bandwidth Memory (HBM)-enabled FPGA. HERA fully saturates the available HBM bandwidth and reduces off-chip memory traffic through the proposed optimizations: First, we propose an adoption of the structural decomposition of key FHE kernels to eliminate irregular and strided HBM accesses and simplify on-chip vector permutation complexity. Second, with contiguous unit-stride HBM accesses, we introduce a novel data layout that enables fully independent access per channel. This eliminates cross-channel communication and the overhead of the built-in crossbar. Third, coupled with our structural decomposition, we develop a Shared Permutation Unit (SPU) that is flexible to handle various vector permutations in FHE with minimal hardware costs, achieving both performance and resource efficiency. Fourth, to reduce HBM traffic, we further propose Hierarchical Memory-centric Optimizations (HMOs). HMOs fuse computation across the FHE stack and maximize data reuse within the FPGA's limited SRAM capacity. Implemented on an Alveo U280, HERA outperforms all prior FPGA works on bootstrapping, a crucial FHE benchmark, achieving 1.2-4.1x speedup. Moreover, HERA delivers an average of 70.9x and 11.4x higher performance density (i.e., throughput per multiplier) than state-of-the-art ASIC-based solutions on two widely adopted applications: secure logistic regression training and encrypted image classification with ResNet-20, respectively.
The modern supply chain ecosystem exposes hardware intellectual property (IP) blocks to diverse confidentiality attacks aimed at reverse engineering (RE), piracy, or the extraction of design secrets. An emerging and potent design solution for IP protection against these attacks, particularly against RE, is the fine-grained redaction of security-critical logic and replacing the redacted logic with lookup tables (LUTs). The LUTs are then programmed in-field, similar to FPGAs, using protected bitstreams, thereby preventing untrusted foundries or test/assembly facilities from mounting RE attacks. The LUT-based redaction paradigm incurs a substantial hardware cost, with area overhead ranging from 70x to 100x and delay overhead from 2x to 5x, while also often necessitating significant alterations to the commercial tool flow for design, verification, and testing. In this work, we propose PROM, a robust fine-grain redaction technique inspired by structured ASIC, that aims to address the limitations of LUT-based redaction with novel overhead optimizations. The redacted security-critical logic is implemented using a library of custom-design PROM cells that are optimized to minimize overheads compared to state-of-the-art redaction techniques while providing strong protection against various RE attacks. We evaluated the proposed redaction technique across a range of open-source benchmarks, achieving robust security with average overheads of 1.42x in area and 1.09x in delay, demonstrating its efficiency and practicality.
Model Recovery (MR) builds physics-guided digital twins from data but runs inefficiently on GPUs due to iterative ODE solvers and memory-bound kernels. We introduce ModEl Recovery IN fpga-based Dynamic Architecture (MERINDA), based on replacing ODE solver with a GRU-based streaming dataflow and co-designs fixedpoint compute and on-chip memory (BRAM tiling, heterogeneous DSP/LUT mapping). On representative MR workloads, MERINDA yields up to 6.3x fewer cycles and 99.3% lower energy than an LTC-based FPGA baseline, enabling real-time edge deployment.
Field-Programmable Gate Arrays (FPGAs) have been shown to be viable for Large Language Model (LLM) deployment, but they remain less competitive than embedded GPUs and NPUs for final edge products. This is largely because existing FPGA-based LLM accelerator prototypes rely on large, expensive FPGA devices to provide sufficient hardware resources for satisfactory performance, whereas edge products are highly cost-sensitive. In this work, we move beyond pure architectural prototyping to evaluate the feasibility of using low-cost FPGAs as the final implementation medium for LLM deployment. We propose Hummingbird+, which encompasses: (1) a compact embedded FPGA-based LLM accelerator designed to deliver comparable inference performance compared to embedded GPUs and NPUs, and (2) a custom Printed Circuit Board (PCB) built around a Zynq UltraScale XCZU2CG/3EG SoC, equipped with 24GB of memory and an expected Bill of Materials (BOMs) under $150 in mass production. Through extensive FPGA-centric optimizations, we significantly reduce the accelerator's resource consumption, enabling deployment on entry-level FPGAs with exceptional cost efficiency. On this platform, we successfully deploy the GPTQ 4-bit Qwen3-30B-A3B LLM, achieving a decoding speed of over 18 token/s and a prefill speed of over 50 token/s without further model compression. To our knowledge, this is the first demonstration of an FPGA-based edge product serving as a practical and cost-effective final implementation medium for LLM deployment.
The computation of highly contracted electron repulsion integrals (ERIs) is essential to achieve quantum accuracy in atomistic simulations based on quantum mechanics. Its growing computational demands make energy efficiency a critical concern. Recent studies demonstrate FPGAs' superior performance and energy efficiency for computing primitive ERIs, but the computation of highly contracted ERIs introduces significant algorithmic complexity and new design challenges for FPGA acceleration. In this work, we present SORCERI, the first streaming overlay acceleration for highly contracted ERI computations on FPGAs. SORCERI introduces a novel streaming Rys computing unit to calculate roots and weights of Rys polynomials on-chip, and a streaming contraction unit for the contraction of primitive ERIs. This shifts the design bottleneck from limited CPU-FPGA communication bandwidth to available FPGA computation resources. To address practical deployment challenges for a large number of quartet classes, we design three streaming overlays, together with an efficient memory transpose optimization, to cover the 21 most commonly used quartet classes in realistic atomistic simulations. To address the new computation constraints, we use flexible calculation stages with a free-running streaming architecture to achieve high DSP utilization and good timing closure. Experiments demonstrate that SORCERI achieves an average 5.96x, 1.99x, and 1.16x better performance per watt than libint on a 64-core AMD EPYC 7713 CPU, libintx on an Nvidia A40 GPU, and SERI, the prior best-performing FPGA design for primitive ERIs. Furthermore, SORCERI reaches a peak throughput of 44.11 GERIS (109 ERIs per second) that is 1.52x, 1.13x, and 1.93x greater than libint, libintx and SERI, respectively. SORCERI will be released soon at https://github.com/SFU-HiAccel/SORCERI.
Microsoft has deployed FPGAs at hyperscale for over a decade, powering diverse application domains and products. While the underlying EDA tool flow remains familiar (synthesis, place & route, and verification), the engineering system that supports FPGA development at Microsoft looks nothing like a traditional hardware flow. Instead, it borrows heavily from modern cloud-scale software practices: Git for version control, Azure DevOps for automated pipelines, extensive regression suites, and daily compiles, effectively adapting the software mantra of "ship every day" to the hardware world as "tape-out every day." The sharpest break from traditional hardware practice, and often the hardest adjustment for hardware engineers joining Microsoft, is that quality comes not only from extensive pre-silicon verification, but even more so from rapid testing of new builds in controlled production environments on real applications. New FPGA images are tested in contained production environments, on real hardware and real applications, giving higher confidence and faster iteration than traditional verification regimes can deliver. This paper describes how this system operates and how it has evolved across multiple FPGA generations, how teams across organizational and geographic boundaries collaborate, the unique challenges of scale, and the cultural and technical shifts required to make FPGAs feel like software. This paper also shares surprising statistics, from the sheer number of daily builds to the compute hours consumed, that highlight what it takes to run FPGA development like a hyperscale cloud service.
Cloud-scale, Artificial Intelligence (AI)-centric deployments are increasingly accelerated and made flexible through Field-Programmable Gate Arrays (FPGAs). Traditional simulation-only verification has often been shown to miss system-level risks that surface late during hardware bring-up. A hybrid verification methodology has therefore been developed in which AI-driven automation is orchestrated with formal connectivity checks to ensure reliable end-to-end signal connectivity and robust reset behavior across heterogeneous FPGA Stock Keeping Unit (SKU) variants. Structured prompts are employed to guide Copilot in generating Python scripts that traverse - Register Transfer Level (RTL) designs, extract signal mappings, and auto-generate timing-aware connectivity assertions in Comma-Separated Values (CSV) format. Precise, context-rich prompts specifying signal roles, hierarchy depth, and reset domains are observed to yield consistent results, whereas generic prompts fail to capture architectural nuances. Reset validation strategies covering Function Level Resets (FLRs), Memory-Mapped Input Output (MMIO) handlers, and firmware-driven resets have been applied in FPGA contexts, while the underlying connectivity assertion framework has been shown to be portable to Application-Specific Integrated Circuit (ASIC) flows with minimal adaptation. Over nine months, the methodology was deployed on multiple hyperscale FPGA platforms, where critical bugs missed by weeks of simulation regressions were surfaced. Integration with commercial formal tools was achieved, scalability to new FPGA variants was demonstrated, and lessons in prompt engineering and cross-domain verification were documented.
