An open source remote diagnostics platform for custom electronics in experimental acquisition setups has been developed, targeting nuclear and high-energy physics (HEP) applications. We aim at enabling remote access to instrumentation hardware prototypes located in radiation-controlled areas by using existent network infrastructures. The platform relies on two components: a graphical user interface (GUI) developed in GNURadio and a remote hardware bridge (HB). The GUI was designed using the GNURadio’s optimized building blocks, ensuring a fluid visualization of real-time pulse traces and energy spectrum. No third-party libraries are used, turning our solution into an easy drop-in tool for instrumentation diagnostics in HEP and radiation-related experiments. Reliable communication between the remote instrument and the GUI is accomplished using TCP/IP, carried out by the HB in case of remote instruments without network interface. A Raspberry PI Zero-W is tested as the HB to demonstrate the few computational resources required for this end.

A method for gamma/neutron event classification based on frequency-domain analysis for mixed radiation environments is proposed. In contrast to the traditional charge comparison method for pulse-shape discrimination, which requires baseline removal and pulse alignment, our method does not need any preprocessing of the digitized data, apart from removing saturated traces in sporadic pile-up scenarios. It also features the identification of neutron events in the detector’s full energy range with a single device, from thermal neutrons to fast neutrons, including low-energy pulses, and still provides a superior figure-of-merit for classification. The proposed frequency-domain analysis consists of computing the fast Fourier transform of a triggered trace and integrating it through a simplified version of the transform magnitude components that distinguish the neutron features from those of the gamma photons. Owing to this simplification, the proposed method may be easily ported to a real-time embedded deployment based on Field-Programmable Gate Arrays or Digital Signal Processors. We target an off-the-shelf detector based on a small CLYC (Cs2LiYCl6:Ce) crystal coupled to a silicon photomultiplier with an integrated bias and preamplifier, aiming at lightweight embedded mixed radiation monitors and dosimeter applications.

Machine learning (ML) models have demonstrated discriminative and representative learning capabilities over a wide range of applications, even at the cost of high-computational complexity. Due to their parallel processing capabilities, reconfigurability, and low-power consumption, systems on chip based on a field programmable gate array (SoC/FPGA) have been used to face this challenge. Nevertheless, SoC/FPGA devices are resource-constrained, which implies the need for optimal use of technology for the computation and storage operations involved in ML-based inference. Consequently, mapping a deep neural network (DNN) architecture to a SoC/FPGA requires compression strategies to obtain a hardware design with a good compromise between effectiveness, memory footprint, and inference time. This letter presents an efficient end-to-end workflow for deploying DNNs on an SoC/FPGA by integrating hyperparameter tuning through Bayesian optimization (BO) with an ensemble of compression techniques.

Computational techniques allow breaking the limits of traditional imaging methods, such as time restrictions, resolution, and optics flaws. While simple computational methods can be enough for highly controlled microscope setups or just for previews, an increased level of complexity is instead required for advanced setups, acquisition modalities or where uncertainty is high; the need for complex computational methods clashes with rapid design and execution. In all these cases, Automatic Differentiation, one of the subtopics of Artificial Intelligence, may offer a functional solution, but only if a GPU implementation is available. In this paper, we show how a framework built to solve just one optimisation problem can be employed for many different X-ray imaging inverse problems.

We present a method for diagnostics analysis for pixelated particle detectors. The method is based on extracting information from the detector in the form of model parameters by using a representative mathematical model. To illustrate the procedure we analyzed real experimental data obtained with the electromagnetic calorimeter ECAL2 of the COMPASS experiment at CERN. Having observed the data, the typical pulses were fitted with a mathematical model. Heat maps were drawn to visualize the distribution of the mean values of each of the fitted parameters. This data visualization technique is useful for highlighting areas with similar behavior and detecting abnormal responses in single cells.

Abstract The HyperFPGA is a scalable SoC-FPGA cluster aimed at exploring new architectures for improved performance and energy efficiency in high-performance computing.Recently, it has become evident that the scaling trend of von Neumann-based supercomputers is unsustainable in terms of energy and performance, stressing a change in the computing paradigm.By exploiting the flexibility, reconfigurability, and programmability offered by the HyperFPGA infrastructure, which combines FPGAs, CPUs, and high-speed general-purpose connectors, it is possible to experiment with novel computing paradigms. The Linux OS and custom drivers, along with a Message Passing Interface (MPI), offer a programmable framework for firmware and task deployment.In addition to describing the design and implementation of the HyperFPGA, we report results obtained by testing its scalability with the N-Queens problem, which is a classic benchmark for evaluating the performance of parallel computing systems.Overall, the testing of the HyperFPGA using the N-Queens problem highlights the platform's ability to handle computationally intensive tasks and demonstrates its suitability for its use in supercomputing.

In recent years, the most powerful supercomputers have already reached megawatt power consumption levels, an important issue that challenges sustainability and shows the impossibility of maintaining this trend. To this date, the prevalent approach to supercomputing is dominated by CPUs and GPUs. Given their fixed architectures with generic instruction sets, they have been favored with lots of tools and mature workflows which led to mass adoption and further growth. However, reconfigurable hardware such as FPGAs has repeatedly proven that it offers substantial advantages over this supercomputing approach concerning performance and power consumption. In this survey, we review the most relevant works that advanced the field of heterogeneous supercomputing using FPGAs focusing on their architectural characteristics. Each work was divided into three main parts: network, hardware, and software tools. All implementations face challenges that involve all three parts. These dependencies result in compromises that designers must take into account. The advantages and limitations of each approach are discussed and compared in detail. The classification and study of the architectures illustrate the trade-offs of the solutions and help identify open problems and research lines.

The COMPASS RICH-1 detector has undergone a major upgrade in 2016 with the installation of four novel MPGD-based photon detectors. They consist of large-size hybrid MPGDs with multi-layer architecture composed of two layers of Thick-GEMs and bulk resistive MicroMegas. A dedicated high voltage power supply system, based on CAEN HV modules, has been built and put in operation: it controls more than 100 HV channels. The system is required to protect the detectors against errors by the operator, monitor voltages and currents at a 1 Hz rate and automatically react to detector misbehavior. It includes also a HV compensation system against environmental pressure and temperature variation to grant the detector stability. The operation of a MPGD based single photon detector poses challenging requirements to the high voltage power supply systems employed in terms of high-resolution diagnostic features and dynamic voltage control. Systems satisfying all the needed features are not commercially available; for this reason a novel single channel high voltage system matching the MPGD needs has been designed and realized. In this article the COMPASS RICH-1 MPGD HV system implementation is described as well as its performance in terms of stability of the novel MPGD-based photon detectors during the physics data taking at COMPASS. The design, implementation and performance of a novel HV power supply system based on DC to DC converters and controlled by a FPGA device is presented. The capabilities of the first prototype of the new single HV channel power supply are illustrated when operated with a MPGD based single photon detector during a test beam exercise. The preliminary result of the multi channel system are briefly discussed.

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The last decade witnessed a renaissance of machine learning for image processing. Super-resolution (SR) is one of the areas where deep learning techniques have achieved impressive results, with a specific focus on the SR of facial images. Examining and comparing facial images is one of the critical activities in forensic video analysis; a compelling question is thus whether recent SR techniques could help face recognition (FR) made by a human operator, especially in the challenging scenario where very low resolution images are available, which is typical of surveillance recordings. This paper addresses such a question through a simple yet insightful experiment: we used two state-of-the-art deep learning-based SR algorithms to enhance some very low-resolution faces of 30 worldwide celebrities. We then asked a heterogeneous group of more than 130 individuals to recognize them and compared the recognition accuracy against the one achieved by presenting a simple bicubic-interpolated version of the same faces. Results are somehow surprising: despite an undisputed general superiority of SR-enhanced images in terms of visual appearance, SR techniques brought no considerable advantage in overall recognition accuracy.

We present an open hardware/software architecture for remote control of Field Programmable Gate Array (FPGA) based Systems on Chip (SoC). These systems, which integrate embedded processors, FPGA fabric, memory blocks and other resources, usually need to be controlled from a computer. The proposed architecture comprises a set of commands, instructions for data movement, and standardized data packets. A minimal set of specifications and design guidelines will effectively separate hardware and software developments granting compatibility to the different subsystems. A simple architectural approach ensures compatibility of computer resident software, embedded processor software, and FPGA designs. The implicit structured design methodology associated with the proposed architecture facilitates remote control as well as maintenance, debugging, and portability among SoC-FPGA vendors. We describe a concrete implementation in order to show how data and instructions can be moved across the whole system.

We present a high-resolution 3-D ( $X$ , $Y$ , $t$ ) imager for time-resolved experiments based on time-to-space conversion. The system uses cross delay line (CDL) detectors for particle identification and a fully configurable digital processor based on field programmable gate arrays (FPGAs) for 3-D image reconstruction. The instrument reaches a spatial resolution of 45 $\mu \text{m}$ full width at half maximum (FWHM) (i.e., 18 $\mu \text{m}$ rms) and a temporal precision of 15 ps rms. The detection rate achieved is 10 Mcps, with a dead time below 7 ns, leading to a global throughput up to 6 Gb/s. In addition to the state-of-the-art performance, the innovative aspect of the presented contribution resides in the complete reconfigurability of the instrument: it is, in fact, the first time that the time-to-digital converter (TDC) used for the time-to-space conversion has been fully implemented in programmable logic (PL), without the use of dedicated application-specific integrated circuit (ASIC) components. This advancement allows to adapt the instrument to the experimental setup without undergoing impractical hardware modifications.

Data logging and complex algorithm implementations acting on multichannel systems with independent devices require the use of time synchronization. In the case of Gas Electron Multipliers (GEM) and Thick-GEM (THGEM) detectors, the biasing potential can be generated at the detector level via DC to DC converters operating at floating voltage. In this case, high voltage isolation buffers may be used to allow communication between the different channels. However, their use add non-negligible delays in the transmission channel, complicating the synchronization. Implementation of a simplified precise time protocol is presented for handling the synchronization on the Field Programmable Gate Array (FPGA) side of a Xilinx SoC Zynq ZC7Z030. The synchronization is done through a high voltage isolated bidirectional network interface built on a custom board attached to a commercial CIAA_ACC carrier. The results of the synchronization are shown through oscilloscope captures measuring the time drift over long periods of time, achieving synchronization in the order of nanoseconds.

Water Cherenkov detectors have been widely adopted as a low-cost technique for cosmic rays (CR) studies. Thus, an existing CR readout system has been chosen as the base DAQ (data acquisition) design, which has been paired to a Neural Network (NN) in order to work as a trace/event discrimination block. We present the compression of two NN architectures for particle classification, targeting a low-end System-on-Chip (SoC). The hls4ml package is used to translate the final NN models into a high-level synthesis project. Both NNs were implemented and tested on Xilinx SoC ZC7Z020 Zynq. A comparison of the accuracy of the detection, resource utilization and latency of the two NNs are presented. The results show the benefits of using compression techniques to deploy a reduced model, which provides a good compromise between efficiency, effectiveness, latency, as well as resource utilization.

This paper describes a custom made high voltage isolated bidirectional network interface for communication among FPGA devices, which are in different power domains. Preliminary performance test and measurements of noise tolerance and stability are presented. A case study of an application regarding a network of multiple single-channel power supply systems for Micro Pattern Gaseous Detectors is portrayed. In order to match the specific system needs of dynamic voltage control, the network interface provides a reliable high voltage decoupling up to 2 kV with reasonable noise tolerance and data transmission rate up to 100 Mbps. The flexibility of the interface allows the implementation of different communication protocols.

One task often encountered in surveillance videos is the recognition of a target—e.g. the license plate of a vehicle. Often, the quality of a single video frame does not permit a reliable recognition. If multiple frames are available, it is possible to combine them in order to generate a single image with lower noise (frame averaging) and/or higher resolution (super-resolution). In order for these techniques to work, it is necessary to accurately estimate the motion of the object of interest in the recorded footage.

Marsi, Stefano Carrato, Sergio De Bortoli, Luca Gallina, Paolo Guzzi, Francesco Ramponi, GiovanniThis paper proposes a method for depth estimation in video sequences acquired by a monocular camera mounted on a mobile platform. The proposed algorithm is able to estimate in real time the relative distances of the objects in the field of view exploiting the parallax effect, provided the platform movement complies with a few constraints. The developed system is designed to operate at the input pixel cadence and is thus applicable to any video resolution. The final architecture, using operators no more complex than an adder and a memory that is just a fraction of a frame memory, can be realized in a low-cost FPGA.