Soft errors can cause detected unrecoverable errors (DUEs) and silent data corruptions (SDCs) in real-time systems, requiring resilience mechanisms that satisfy both timing and reliability requirements. Existing fault-aware scheduling approaches typically account for re-execution using worst-case execution time (WCET), which is safe for schedulability analysis but can hide runtime re-execution opportunities created by shorter actual execution times or early DUE detection. This paper presents a deadline-bounded re-execution model using Lingua Franca (LF), where re-executions are treated as deadline-aware attempts rather than statically reserved WCET replicas. The proposed model triggers re-execution based on DUE detection or estimated SDC probability of completed executions, while LF deadline handlers make insufficient slack a first-class observable outcome. We implement an LF-based simulation framework to study how DUEs, SDCs, voting, deadline violations, and re-executions interact under soft error resilience policies.
Radar receivers require precise DDC filtering to suppress clutter, yet the FIR stage often dominates FPGA power and resources. This letter presents a coefficient-sensitive approximate FIR architecture that relaxes precision for low-sensitivity taps while retaining full-precision for critical coefficients. Implemented on a Zynq UltraScale+ MPSoC, the design reduces area by 22% and power by 20% with minimal DSP usage. Despite approximation, it maintains a –62 dB stopband, ≤ 0.03 dB ripple, and –44 dB NMSE. These results validate that controlled approximation preserves radar-grade spectral fidelity while enabling power-efficient, scalable DDC for next-generation reconfigurable systems.
Haze degrades visibility and adversely affects image-processing applications, such as drone surveillance, autonomous driving, traffic and security monitoring. Although CNN-based dehazing achieves superior restoration quality, it is computationally intensive. Therefore, their implementation on resource-constrained platforms is challenging for real-time operations. To address this issue, we present a lightweight CNN-based image dehazing architecture and hardware accelerator for real-time deployment on an FPGA platform. The proposed design is accelerated using dilated depthwise separable convolution, efficient weight handling and resource-folding technique. The model is implemented using High-Level Synthesis with Vitis HLS. Experimental results show that the proposed architecture achieves a throughput of 119 frames per second at 640 × 480 resolution, meeting real-time processing requirements while maintaining high image restoration quality with an average PSNR and SSIM of 25.69 dB and 0.937, respectively, while utilizing only 2,943 parameters. The hardware implementation also demonstrates efficient utilization of FPGA resources, with approximately 13% LUT, 9% BRAM, 7% Flip-Flops, and 19% DSP usage on the ZCU104-G target device. The source code is publicly available at: https://github.com/AnirudhBhogi/Nano-DRUnet.
The exponential growth of Industrial Internet of Things (IIoT) devices has created a computational bottleneck for blockchain-based data authentication, overwhelming traditional edge gateways. This letter proposes a high-performance, energy-efficient heterogeneous edge gateway designed for IIoT consensus acceleration. By leveraging a hardware-software co-design strategy, we offload the computation-intensive Ed25519 signature verification to the FPGA while managing the Practical Byzantine Fault Tolerance (PBFT) consensus logic on the Central Processing Unit (CPU). A novel pre-scheduled finite-field multiplier and a state driven datapath are introduced to maximize the execution efficiency of cryptographic operations. The proposed system is implemented on the Xilinx Kria KV260 platform. Experimental results demonstrate that the accelerator achieves a signature verification latency of 0.11 ms and a system-level consensus throughput of 384 transactions per second (TPS). With a total power consumption of only 8.3 W, the proposed design offers a superior balance between performance and energy efficiency compared to existing software-based solutions.
Signal processing parameters in real-time logging-while-drilling (LWD) systems, such as filter ranges and orders, are typically fixed during operation because manual intervention is infeasible. These static settings often fail to adapt to formation changes with depth. This letter introduces an online-adaptive algorithm to overcome these constraints by incorporating two stages into the standard slowness-time coherence (STC) workflow: (1) automated identification of component-wave frequency bands, and (2) dynamic adjustment of FIR filter orders based on real-time spectral amplitude ratios. Experimental results show that this approach maintains reliable slowness extraction across varying downhole conditions without manual tuning, making it suitable for resource-constrained LWD environments. Implementation on a PSoC platform confirms that the algorithm satisfies the stringent real-time, memory, and power requirements of downhole embedded systems.
Neural networks have enabled advances across various domains, but their large resource requirements remain a challenge. Quantization is a promising approach for reducing the computational complexity of models. To make proper use of quantized networks, special hardware is required that supports operations at low bit-widths. We present a hardware-software co-design, including an FPGA-based MAC unit that uses bitshifts at two levels of precision, with doubled throughput at low precision. Our quantization-aware training framework prepares models for use with the MAC unit by logarithmically quantizing them and applying several quantization techniques that reduce the required hardware. We are able to run 90% of operations during inference with 2-bit weights and 4-bit activations, while reducing accuracy by only 1.72 percentage points compared to full precision.
This paper presents a hardware-efficient memory architecture for high-throughput, low-latency output reordering of continuous-flow 4096-point FFT/IFFT cores in 5G embedded systems. To meet real-time processing requirements, a continuous-flow reordering scheme based on conflict-free memory addressing (CFMA) is proposed, enabling parallel access to multiple memory banks. The reordering block is seamlessly integrated with the FFT/IFFT core to generate naturally ordered FFT/IFFT outputs without interrupting the data stream. The synthesized netlist of the proposed architecture, generated using the Cadence Genus tool targeting a UMC 65-nm CMOS process at a clock frequency of 250 MHz, is functionally validated using MATLAB-generated reference outputs. The design achieves a latency of 3.40 μs and a sustained throughput of 4 GS/s, corresponding to a 29.03% throughput improvement over the best reported literature.
Distributed cyber-physical systems increasingly demand peer-to-peer operation to avoid single-point-of-failure bottlenecks in centralized coordination. However, extending deterministic semantics to decentralized systems where federates dynamically join and leave remains open. This paper extends our prior work on transient federates in Lingua Franca (LF) to decentralized coordination, which eliminates the central Run-Time Infrastructure (RTI) as the time arbiter. We analyze the interactions between timing constructs in decentralized LF federations, characterize the conditions under which a transient federate may safely join a running federation and validate both experimentally. A key finding is that the join protocol shifts most coordination work from the RTI to the joining federate itself.
Embedded streaming speech enhancement must meet real-time latency targets under a limited on-chip SRAM budget. In such settings, deployment feasibility is constrained not only by compute throughput but also by the resident memory required for model parameters and intermediate data. This letter presents a low-SRAM fully streaming accelerator for causal Mamba-based speech enhancement. The model and hardware are jointly tailored for bounded-memory deployment. To reduce parameter storage and runtime buffering, the design removes local convolution and gating and replaces fully connected projections with grouped 1×1 pointwise operators. This architecture avoids storing full-frame intermediate activations. A 40-nm post-layout implementation occupies 0.722 mm2 and uses 16.625 kB SRAM for state retention and decoder accumulation. At 0.9 V and 100 MHz, it achieves 6.24 ms latency for 10-ms frames at 16 kHz. Field-programmable gate array (FPGA) prototyping reports a latency of 6.28 ms and a 67.06× speedup over an ARM Cortex-A9 baseline, confirming sub-frame real-time operation.
Small-zone Zoned Namespace (ZNS) SSDs are increasingly adopted in memory-constrained embedded storage systems for their superior isolation and reduced DRAM overhead. However, to compensate for limited per-zone bandwidth, these devices typically rely on parallel data striping, which inadvertently mixes data with disparate lifetimes, resulting in severe fragmentation. This paper proposes ZAPI, a lightweight, passive invalidation-driven zone-allocation framework for embedded LSM-tree-based stores. ZAPI identifies that passive invalidation triggered by key-range overlaps with lower LSM-tree levels as the dominant determinant of data lifetime in small-zone architectures. By implementing a low-complexity, bidirectional, overlap-aware clustering mechanism, ZAPI effectively segregates short-and long-lifetime data without taxing the limited computational resources of embedded controllers. Experimental evaluations using the NVMeVirt simulator show that, compared with level-based allocation, ZAPI reduces valid data migration by up to 41.50%, lowers the unnatural invalidation rate by up to 27.78%, and reduces reset zones by up to 16.52%. Compared with the ZenFS baseline, the reduction in valid data migration reaches up to 62.09%. These improvements reduce redundant background garbage collection and can improve the endurance of embedded ZNS SSDs.
Bounded Model Checking (BMC) generates a monotonically growing sequence of CNF formulas by incrementally unrolling a transition relation. While the quantitative growth is well understood, the qualitative evolution of formula structure across unrolling frames has not been systematically characterized. We present an empirical study that tracks topological SATzilla features across up to 50 unrolling frames for HWMCC’24 and HWMCC’25 industrial benchmarks. To ensure that our metrics capture purely structural change, we rigorously filter the 401 SATzilla features down to 348 topological features by excluding temporal, problem-size, and solver-performance metrics. Our analysis reveals: (i) a sharp shift in structure during the early frames followed by prolonged gradual evolution, with global mean drift decaying but not vanishing; (ii) consecutive-frame cosine similarity approaching 0.9–0.95 but not converging to unity; and (iii) only 28% of benchmarks converging to within a 10% relative distance of their final observed state, and relaxing this threshold to 20% increases convergence to only 51% of benchmarks. These results demonstrate that BMC formulas remain topologically dynamic throughout most of the unrolling process, motivating structure-aware adaptive verification strategies.
Lingua Franca (LF) is a coordination language for building deterministic concurrent software using components called reactors, whose behavior is defined by a set of event-driven reactions. Federated reactors carry this determinism across distributed nodes and are therefore called federates. A federation keeps its deterministic timing as long as the links interconnecting the federates obey a maximum latency, called maxwait, specified at design time. LF’s runtime for microcontroller-class devices already carries federations over wired links and over IP, but not over a low-power radio, whose probabilistic behavior makes the selection of maxwait non-trivial. Mobile IoT nodes, wearables and small sensors are therefore hard to integrate. We close this gap by adopting a connection-oriented Bluetooth Low Energy (BLE) link, which is itself time-triggered: a configurable periodic transmit schedule with automatic retransmission. Therefore, fixing a retransmission budget yields a deterministic latency bound for every message delivered within the budget, and tardy handling for the rest. We derive a closed-form latency LBLE, accounting for the worst-case number of retransmissions needed to achieve it with a given target reliability, and establish a method to automatically synthesize BLE configurations that satisfy a specified maxwait. We finally evaluate such links and present an implementation in LF’s Reactor-UC.
This paper presents a methodology for optimizing Montgomery-reduction-based modulo-arithmetic circuits by identifying invariant properties of intermediate computations, eliminating redundant operations arising from repeated adder structures and two’s-complement cancellations, and simplifying carry propagation through algorithm-aware transformations. The resulting customized implementations substantially reduce circuit complexity beyond what is achievable using conventional synthesis from Montgomery algorithms. We evaluate the proposed methodology on combinational Montgomery reduction-based modulo-arithmetic circuits for NIST-standard prime moduli. Experimental results show that our approach achieves substantial reductions in circuit area and critical-path delay compared with both data-flow-based implementations and conventional synthesis methods using observability don’t-cares.
As Deep Neural Network (DNN) applications drive the development of intelligent connected vehicles (ICV), there is a clear need for efficient and reliable DNN processing. Vehicular Edge Computing (VEC) is a promising paradigm to meet such demand. However, low communication capacity in VEC limits the latency benefits of collaborative DNN computing. Introducing quantization to DNN in VEC remains challenging due to the need for real-time decision-making and accuracy guarantees in dynamic computing environments. This letter proposes a desig-ntime deep reinforcement learning-based strategy for DNN quantization in VEC. The strategy adapts to dynamic communication and computing environments at runtime while complying with accuracy drop constraints. Compared to greedy strategies, our results show up to 21% latency saving and 44% reduction of channel occupancy in a two-vehicle setting. These results advance the feasibility of fast and reliable DNN inference for safety-critical intelligent connected vehicle applications.
Exploiting homomorphic-friendly symmetric ciphers is regarded as one of the primary approaches for embedded systems to achieve confidentiality, integrity and authentication to prevent malicious cyberattacks. YuS, a novel Homomorphic Encryption (HE) friendly stream cipher published at IEEE TIT in 2025 [1], exhibits promising application prospects for the security and privacy protection in embedded systems. To better find potential security vulnerabilities and enhance the security of embedded systems employing the YuS cipher, this letter proposes a novel differential fault attack (DFA) against the YuS cipher. By injecting a random word-based fault, we extract the information leakage of the internal state of the YuS cipher for the first time, and then leverage this leakage to launch a targeted DFA. For the recommended instances of YuS (YuS-5 and YuS-6), our attack is practical and requires only one block of normal keystream and two blocks of faulty keystream. The proposed attack imposes no restrictions on the fault injection location and also allows for a loose fault injection precision (i.e., faults only need to be injected at the word-level), thus making it highly feasible in real-world deployment scenarios. Furthermore, to the best of our knowledge, this constitutes the first known third-party attack against the YuS cipher.
This work validates the applicability of the Middleton Class A (MCA) model for representing underwater impulsive noise through the analysis of signals that incorporate realistic channel effects. Simplified physically motivated time-domain noise generators were developed based on the model’s original hypotheses, enabling the simulation of underwater environments that include marine and receiver noise, as well as attenuation and reverberation effects. Additionally, real seabed recordings were employed for comparison and validation. The results indicate that the MCA model provides a suitable approximation for representing impulsive underwater noise under the evaluated conditions.
Hamming Quasi-Cyclic (HQC) is an emerging code-based post-quantum Key Encapsulation Mechanism (KEM) standardized by the US National Institute of Standards and Technology (NIST) in 2025. The implementation aspects of HQC are less researched since its inception, unlike its lattice counterparts (e.g., Kyber). This work focuses on the fine-grained parallel implementation of HQC on Graphics Processing Units (GPUs) to achieve high throughput and low latency key encapsulation and decapsulation. The main focus is to optimize the GF(2) polynomial multiplication in HQC which takes up ≈90% of the computation time. To overcome this bottleneck, a highly optimized 64-bit carry-less multiplication technique targeting GPU architecture is proposed, effectively improving the throughput of base multiplication in HQC by 2.21×. Following this, parallel implementation techniques were proposed to optimize the Karatsuba and Reed-Soloman algorithm on a low-latency finegrained HQC implementation, which is useful for small batches of workload. This implementation achieved 42172, 26514 and 49384 Encapsulation/s, 25254, 19018 and 35502 Decapsulation/s, on RTX5070, A100 and H100 respectively.
Real-time video transmission on resource-constrained edge devices demands efficient compression, security, and low computational overhead. This work presents a performance-oriented AES-inspired encryption for a secure video processing pipeline that integrates an optimized H.264-derived encoder. The encoder reduces redundant Discrete Cosine Transform computations by exploiting inter-frame correlations, which reduces CPU utilization while preserving application-level video quality. The proposed encryption design, pAES, increases data-level parallelism using GPU-friendly operations to achieve high throughput. Experimental results on NVIDIA Tegra X1 SoC reduces latency by 10.8% in CPU utilization, improve compression efficiency, and 4.2× increase in throughput compared to standard H.264+AES implementations. The results indicate that the proposed pipeline effectively supports secure, real-time video analytics on edge platforms.
This letter presents EyesOn, an open-source eye-gaze interaction framework that transforms ordinary webcams into accessibility tools for individuals with motor impairments. Unlike conventional eye-tracking systems that rely on pixel-level gaze accuracy, EyesOn adopts a region-based interaction paradigm that maps gaze estimates into quantized interface regions, improving robustness while reducing computational requirements. The framework combines gaze-region mapping, temporal stabilization, and blink-based selection to enable reliable hands-free control on commodity hardware. Experimental results demonstrate real-time operation at up to 40 FPS on a Raspberry Pi 5 using an ONNX-optimized and Hailo-assisted pipeline. A region-level evaluation achieved 89.71% interaction accuracy across four interface regions, showing that reliable gaze-based accessibility can be achieved without specialized hardware.
Protecting edge-AI model parameters stored in off-chip memory requires authenticated encryption with associated data (AEAD), yet the architectural implications of integrating AEAD into ultra-low-power RISC-V inference pipelines remain largely unexplored. Through cycle-accurate measurements on an industrial RISC-V processor and overhead evaluation on inference of five practical quantized edge models, we identify three fundamental challenges. First, a cipher–architecture mismatch: under identical pure-software conditions on a scalar RISC-V pipeline, ciphers whose primitives align with the processor word width (ASCON, ChaCha20-Poly1305) outperform those designed for minimal hardware area (Grain-128AEAD) by up to 200× in cycles per byte. It indicates that the optimal cipher choice is tightly coupled to the implementation point along the software–hardware spectrum. Second, a decryption bottleneck crossover: two lightweight custom RISC-V instructions reduce ASCON decryption to 20 cycles/byte (3.2× speedup), possibly shifting the inference pipeline from decryption-bound to other bottlenecks. Third, layer-size non-uniformity: per-layer parameter sizes in modern edge models span over five orders of magnitude, creating an open scheduling challenge for fixed-throughput cipher engines. This work presents an architectural characterization, defines concrete design guidance, and identifies open problems for secure edge-AI architectures.
