Current Cyber-Physical Systems (CPS) are fundamentally reactive, and current programming methods suffer from compatibility and concurrency bugs due to manual software integration. Although Lingua Franca’s (LF) reactor model ensures deterministic execution, making CPS applications safer and more reliable, existing runtimes such as reactor-c struggle to support resource-constrained embedded devices. This paper presents reactor-uc’s code generator and macro interface, a light-weight runtime that uses object-oriented C patterns and a macrobased interface to eliminate dynamic memory allocation and simplify code generation. Evaluation results show that reactoruc produces code that is one-third the size and has half the cyclomatic complexity of reactor-c, as well as smaller binaries, while maintaining comparable performance on benchmarks.
Decentralized peer-to-peer (P2P) IoT protocols expose failure modes that appear only across multiple nodes in real environments. Simulation abstracts these failure modes away; ad hoc bench setups capture them but produce no structured, comparable measurements. This paper introduces an open-source experimental platform designed to bridge the gap between simulation and real-world deployment. The architecture is built on three properties: logical separation between a data plane and a control plane, so that experiment orchestration and metric collection do not traverse the protocol’s logic path; automated compile-time identity assignment coupled with dynamic runtime experiment control to support topologies up to a compile-time peer-count ceiling from a single source tree; and a modular framework of self-contained Python experiment scripts feeding a structured, per-node, per-round metrics pipeline. We validate the platform using the CHIRP firefly-inspired pairing protocol across 14 experiments at 2 to 10 nodes. Node activation is driven by a controller JOIN command; contrasting simultaneous (bulk) with staggered JOIN, the structured metrics surface a previously-undocumented, preliminary bulk-initialization failure mode — 28 to 74 spurious peer-pairing attempts per single run under bulk JOIN versus 0 to 14 under staggered JOIN, where such spurious pairings waste airtime and transiently corrupt peer tables. The platform and all experimental modules are available online [1].
Background subtraction is a critical component in real-time video surveillance systems, especially when implemented on resource-constrained embedded platforms. Existing methods often face a trade-off between robustness, consistency and processing speed. We introduce Embedded Codebook-Based Background Subtraction (ECoBS), which combines perpixel codebook modeling, two-level matching, Additive Increase Multiplicative Decrease (AIMD) based contour filtering, and a block-based adaptive update strategy. The proposed method is implemented using parallel pixel processing, which allows rea-time processing without requiring GPU support. Experimental evaluation in CDnet 2014 video sequences shows that ECoBS achieves an overall F-score of 0.8869, outperforming SuBSENSE (0.7857) and PAWCS (0.7943), while achieving processing speed suitable for embedded systems.
Block floating point (BFP) quantization and pruning are effective techniques for reducing the computation and memory footprint of convolutional neural networks (CNNs). However, their hardware integration is challenging because sparsity introduces irregular index-driven data access, whereas BFP relies on regular block-based exponent sharing. This letter presents BFP_S, a sparse-aware BFP accelerator for efficient CNN inference on FPGA. The core design is a sparse BFP multiply-accumulate (MAC) unit that aligns compressed nonzero weight indices with activation mantissas. This preserves shared-exponent computation within each BFP block and enables direct mapping of nonzero operands to MAC operations. Based on this design, a customized accelerator and dataflow are developed to skip redundant operations and reduce switching activity. Implemented on a Xilinx ZCU102 FPGA, BFP_S achieves up to 2.8× higher power efficiency than representative prior accelerators while maintaining comparable inference accuracy.
In this paper, an efficient 16-point radix-4 FFT architecture is proposed. The proposed design takes advantage of the repetition of specific values in the real and imaginary components of the twiddle factors in the 16-point radix-4 FFT to minimize arithmetic operations. This simplification also allows resource sharing to further reduce hardware complexity. FPGA implementation results show that the proposed architecture achieves real-time performance while reducing power consumption by 51.3% and DSP block utilization by 66.6% compared with the conventional hardware. Furthermore, it achieves the lowest Power-Delay Product (PDP) of 17.5 nJ among all evaluated 16-point radix-4 FFT designs.
