We report the characteristics of atmospheric chemical vapor deposition grown bilayer graphene transistors fabricated on ultra-scaled (10 nm) high-kappa dielectric aluminum oxide (Al2O3) at elevated temperatures. We observed that the drive current increased by >400% as temperature increased from room temperature to 250 degrees C. Low gate leakage was maintained for prolonged exposure at 100 degrees C but increased significantly at temperatures > 200 degrees C. These results provide important insights for considering chemical vapor deposition graphene on aluminum oxide for high temperature applications where low power and high frequency operation are required. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

A low-cost and simple atmospheric chemical vapor deposition (APCVD) based double-layer graphene is used to study its transport phenomena at temperature as high as 250 °C. Beyond this temperature the fabricated graphene transistor fails to function, indicating areas of improvements related to dielectric engineering and device isolation. At the same time, it is interesting to note that such low band gap graphene operated fully even at gate current densities as high as 1 A/cm2 and channel current densities as high as 1 MA/cm2 at 250 °C. The study by Ramy M. Qaisi et al. (pp. 621–624) can be a cornerstone to explore graphene as an alternate low-cost material in place of traditional GaN and SiC based power devices for harsh environment application.

The brain's cortex is folded and thus can accommodate billions of neurons in an ultra-compact area. On page 2794, M. M. Hussain and co-workers demonstrate the world's first state-of-the-art non-planar 3D FinFET on flexible silicon-on-polymer using a CMOS compatible process to enable brain-architecture-inspired future ultra-high performance electronics-based computer design. This approach can also result in stylish product design in the near future for ultra-mobile devices and consumer electronics.

An industry standard 8'' silicon-on-insulator wafer based ultra-thin (1 μm), ultra-light-weight, fully flexible and remarkably transparent state-of-the-art non-planar three dimensional (3D) FinFET is shown. Introduced by Intel Corporation in 2011 as the most advanced transistor architecture, it reveals sub-20 nm features and the highest performance ever reported for a flexible transistor.

Nanoelectromechanical (NEM) switch is an interesting ultra-low power option which can operate in the harsh environment and can be a complementary element in complex digital circuitry. Although significant advancement is happening in this field, report on ultra-low voltage (pull-in) switch which offers high switching speed and area efficiency is yet to be made. One key challenge to achieve such characteristics is to fabricate nano-scale switches with amorphous metal so the shape and dimensional integrity are maintained to achieve the desired performance. Therefore, we report a tungsten alloy based amorphous metal with fabrication process development of laterally actuated dual gated NEM switches with 100 nm width and 200 nm air-gap to result in <;5 volts of actuation voltage (V pull-in ).

Chemical vapor deposition based graphene grown on copper foil is attractive for electronic applications owing to its reliable growth process, large area coverage, and relatively defect free nature. However, transfer of the synthesized graphene to host substrate for subsequent device fabrication is extremely sensitive and can impact ultimate performance. Although ultra-high mobility is graphene's most prominent feature, problems with high contact resistance have severely limited its true potential. Therefore, we report a simple poly-(methyl methacrylate) based transfer process without post-annealing to achieve specific contact resistivity of 3.8 x 10(-5) Omega cm(2) which shows 80% reduction compared to previously reported values. (c) 2013 AIP Publishing LLC.

We report observation of energy reversible switching from amorphous metal based nanoelectromechanical (NEM) switch. For ultra-low power electronics, NEM switches can be used as a complementary switching element in many nanoelectronic system applications. Its inherent zero power consumption because of mechanical detachment is an attractive feature. However, its operating voltage needs to be in the realm of 1 volt or lower. Appropriate design and lower Young's modulus can contribute achieving lower operating voltage. Therefore, we have developed amorphous metal with low Young's modulus and in this paper reporting the energy reversible switching from a laterally actuated double electrode NEM switch.

We demonstrate a buried contact based novel test structure for direct contact resistivity measurement of graphene-metal interfaces. We also observe excellent contact resistivity ~1 μO-cm 2 without any additional surface modification suggesting that the intrinsic Au-graphene contact is sufficient for achieving devices with low contact resistance. The chemical mechanical polishing less test structure and data described herein highlights an ideal methodology for systematic screening and engineering of graphene-metal contact resistivity to enable low power high speed carbon electronics.

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

This letter reports, for the first time, heterogeneous integration of bismuth telluride (Bi2Te3) and antimony telluride (Sb2Te3) thin-film-based thermoelectric (TE) devices on a CMOS substrate. The TE films are deposited on a silicon-on-insulator substrate with FinFETs (3-D multiple gate field effect transistors) via a characterized TE-film coevaporation and shadow-mask patterning process using predeposition surface treatment methods for reduced TE-metal contact resistance. As a demonstration vehicle, a 2 x 2 mm(2)-sized integrated planar thermoelectric generator (TEG) is shown to harvest 0.7 mu W from 21-K temperature gradient. Transistor performance showed no significant change upon post-CMOS TEG integration, indicating, for the first time, the CMOS compatibility of the Bi2Te3 and Sb2Te3 thin films, which could be leveraged for realization of high-performance integrated micro-TE harvesters and coolers.

SUMMARYIn this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.

Graphene is a semi-metallic, transparent, atomic crystal structure material which is promising for its high mobility, strength and transparency - potentially applicable for radio frequency (RF) circuitry and energy harvesting and storage applications. Uniform (same number of layers), continuous (not torn or discontinuous), large area (100 mm to 200 mm wafer scale), low-cost, reliable growth are the first hand challenges for its commercialization prospect. We show a time variant uniform (layer control) growth of bi- to multi-layer graphene using atmospheric chemical vapor deposition system. We use Raman spectroscopy for physical characterization supported by electrical property analysis.

The performance and reliability of (1 0 0) and (1 1 0) sidewall, silicon-on-insulator (SOI) FinFETs with a Hf-based gate dielectric were evaluated. Unlike the typical planar MOSFET mobility orientation dependence, (1 1 0) FinFET sidewalls do not impair electron mobility and result in good short channel performance compared to (1 0 0) FinFET sidewall devices. Hot carrier injection (HCI) degradation was also investigated with nMOS and pMOS high-kappa FinFETs on both sidewall surface orientations. Impact ionization at the source, as well as at the traditional drain side, was found to enhance HCI degradation when gate voltage (V-g) = drain voltage (V-d). The degradation becomes more pronounced as the gate length decreases, with a negligible dependence on substrate orientation. However, the orientation dependence of negative bias temperature instability (NBTI) on FinFETs demonstrates that the (1 1 0) orientation is slightly worse than (1 0 0). The kinetics of Delta N-rr(t) under negative bias stress conditions suggests the interface trap density (N-rr) is generated by a mechanism similar to that in planar devices. (C) 2012 Elsevier Ltd. All rights reserved.

We report on terahertz detection (from 0.2 THz to 2.4 THz) by Si FinFETs of different widths (with 2, 20, and 200 fins connected in parallel). FinFETs (with a small number of fins and with feature sizes as short as 20 nm to 40 nm) showed a very high responsivity (far above that previously measured for standard CMOS). We explain this improvement by negligible narrow channel effects.

We report on the design and modeling of novel nano electromechanical switches suitable for implementing reset/set flip-flops, AND, NOR, and XNOR Boolean functions. Multiple logic operations can be implemented using only one switching action enabling parallel data processing; a feature that renders this design competitive with complementary metal oxide semiconductor and superior to conventional nano-electromechanical switches in terms of functionality per device footprint. The structural architecture of the newly designed switch consists of a pinned flexural beam structure which allows low strain lateral actuation for enhanced mechanical integrity. Reliable control of on-state electrical current density is achieved through the use of metal-metal contacts, true parallel beam deflection, and lithographically defined contact area to prevent possible device welding. Dynamic response as a function of device dimensions numerically investigated using ANSYS and MatLab Simulink.

Electronic structure heterogeneities are ubiquitous in two-dimensional graphene and profoundly impact the transport properties of this material. Here we show the mapping of discrete electronic domains within a single graphene sheet using scanning transmission X-ray microscopy in conjunction with ab initio density functional theory calculations. Scanning transmission X-ray microscopy imaging provides a wealth of detail regarding the extent to which the unoccupied levels of graphene are modified by corrugation, doping and adventitious impurities, as a result of synthesis and processing. Local electronic corrugations, visualized as distortions of the π*cloud, have been imaged alongside inhomogeneously doped regions characterized by distinctive spectral signatures of altered unoccupied density of states. The combination of density functional theory calculations, scanning transmission X-ray microscopy imaging, and in situ near-edge X-ray absorption fine structure spectroscopy experiments also provide resolution of a longstanding debate in the literature regarding the spectral assignments of pre-edge and interlayer states.

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.

We present a design, simulation results and fabrication of electromechanical switches enabling parallel data processing and multi functionality. The device is applied in logic gates AND, NOR, XNOR, and Flip-Flops. The device footprint size is 2μm by 0.5μm, and has a pull-in voltage of 5.15V which is verified by FEM simulation.