In the flip-chip interconnection technology, Cu–Cu bonding is one of the key technologies. Currently, the industry commonly uses hot-press bonding to achieve high-density Cu–Cu interconnection. However, this method requires high temperature, high pressure, and high vacuum environment, and the process conditions are relatively harsh. In the semiconductor manufacturing industry, electroplating technology is widely used, such as the preparation of copper column bumps, redistribution layers, and silicon vias, which often take place in a room temperature and low-pressure environment. This article proposes to use electroplating technology to achieve bonding interconnection between the chip and the copper substrate. First, the COMSOL is used to simulate and analyze the electroplating process between the chip and the board under the synergistic effect of the flow field and the accelerator and inhibitor. Then, electroplating bonding experiments were carried out, and the results showed that under the action of additives, the electroplating bonding showed a “from inside to outside” preference for deposition, which is consistent with the convection-dependent adsorption mechanism. Under strong convection conditions, most bump bonding can be achieved, and the morphology of the bonded bumps is good. The overall shear strength of the chip bump reaches 101.8 MPa, which has good process superiority and electromechanical reliability compared with tin-based solder bonding. At the same time, combined with the shear fracture surface diagram, it can be seen that the electroplating primarily deposits at the bottom of the copper pillar, indicating that more reliable interconnection technology can be achieved through optimization of the bonding process in the future.

With the development of packaging devices toward high performance and high density, electronic devices are subjected to thermo-electric stresses under service conditions, which has become a particularly important reliability problem in micro-electronics packaging. The reliability of the chip under thermo-electric stresses is studied in this paper. First, thermo-electric coupling experiments were carried out on two solder joint structures of Ni/Sn3.5Ag/Cu and Ni/Sn3.5Ag/Ni. The interface evolution of solder joints under different current densities was analyzed. The reliability of the two structures under thermo-electric stresses was compared and analyzed. After that, three-dimensional finite element analysis was employed to simulate the current density, Joule heat, and temperature distribution of the flip chip. Finally, through the combination of experiment and simulation, the distribution of Joule heat and temperature of the chip was analyzed. The results show that the Ni/Sn3.5Ag/Ni structure has better reliability than the Ni/Sn3.5Ag/Cu structure under thermal-electric coupling. In addition, when the Ni layer was used as the cathode side, the constant temperature applied on the chip was 150 degrees C, and the current density was higher than 5 x 10(4) A/cm(2), the dissolution failure of the Ni layer occurred in two structures. Because the higher current density generated a large amount of Joule heat where the current was crowded, resulting in excessively high temperature and rapid dissolution of the Ni barrier layer.

In modern society, electronic equipment continues to develop in the direction of miniaturization and multifunction. In order to meet this requirement, packaging technology has gradually evolved from “2-D planar packaging” to “3-D packaging.” The realization of the flip-chip bonding process and the thermal cycle reliability of the 3-D stacked structure are discussed in this article. First, to stack three substrates and a small size chip together, the flip-chip bonding machine was used to vertically stack the chips in the $Z$ -direction. Then, the finite element software was used to analyze the thermal stress distribution of the overall structure under the thermal cycle load, and the life of the critical solder joints in the package was predicted. The simulation results show that, compared to the solder joints between the substrates, the copper pillar bumps of the small-size chip had a longer life.

The effect of V alloying on the creep properties of the Zn-10Al alloy at ambient temperature was investigated. V alloying significantly refined the Zn-10Al grains, and a new Al3V phase was observed. After cold deformation and heat treatment, the steady-state creep rate of the Zn-10Al-0.5 V alloy at 0.2 center dot sigma(0.2) and ambient temperature was 4.65 x 10(-6)h(-1), and decreased with increasing V content. The Zn-10Al-0.5 V alloy had a fine grain structure and maintained a favourable creep resistance owing to the dispersed Al3V, which pinned dislocations and hindered grain boundary migration.

采用XRD、SEM、流动性能测试和硬度测试等方法,研究Cu和Si质量分数对铸态Zn-14Al合金组织与性能的影响.研究结果表明:在铸态Zn-14Al合金中,Cu质量分数为4％～7％时,Cu相主要为?(CuZn4),其弥散分布在α-Al树枝晶间;而Cu质量分数为10％～13％时,存在2种含Cu相,分别为?相和呈五角星形的θ(CuAl2)相;随着Cu质量分数提高,合金中的共晶组织增多,合金的流动性能提高;含Cu相维氏硬度比基体相(α,η)维氏硬度高约204,Cu质量分数从0提高至13％时,合金中的硬质含Cu相增多,第二相强化效果显著,抗拉强度和硬度分别提高了17.7％和48.7％.合金中的Si相主要以初晶硅的形式存在,随着Si质量分数的提高,Si相聚集成团生长,合金的硬度略微提高,但流动性能和抗拉强度下降.Zn-14Al-10Cu合金表现出最优的综合力学性能,即布氏硬度为140.8,抗拉强度为398.33 MPa,断后伸长率为4.1％,且该合金兼具良好的流动性能,可作为汽车零件试制模具用锌合金材料.