Electroplating bonding technology enables high-density, room-temperature, and pressure-free Cu-Cu interconnection, making it a key focus in advanced packaging. This study investigates two accelerators, sodium polystyrene sulfonate (SPS) and thiazolidine dithiopropane sulfonic acid sodium salt (SH110). A micro-Cu pillar array bonding process is proposed, and finite element simulation reveals the "conformal deposition" characteristic in single-accelerator systems. Experiments show that single-accelerator systems yield thicker deposits with limited bonding quality. Single bumps exhibit conformal deposition, and single-row plating presents a "thick-at-entrance and thin-in-middle" feature. After convection enhancement (from 100 mu L/min to 200 mu L/min), the SPS system shows a 30.5 % increase in non-uniformity of plating thickness, and the interconnection success rate rises from 31.3 % to 100 %. In contrast, the SH110 system shows a 56.7 % decrease in non-uniformity and a drop in success rate from 50 % to 31.3 %. These results provide new insights for optimizing Cu-Cu electroplating bonding processes.

Micro/nano structures on metal surfaces were widely used in many fields due to their unique appearance and morphology. This study presented a simple and environmentally friendly electroless deposition method utilizing sodium hypophosphite to synthesize Ni-P microcone coatings. A systematic investigation was conducted on the effects of key process parameters on coating morphology, P content, and crystalline orientation. The results demonstrate that Ni-P coatings with different morphologies can be obtained by adjusting the process parameters. Crucially, the formation of these microcones was found to require a low phosphorus content of approximately 3.5 wt.%. And the Ni-P microcone coating exhibited a strong preference orientation of Ni(1 1 1). Based on the microscopic observation of the microcone structure and crystallographic analysis, it was suggested that the growth mechanism of Ni-P microcone coatings may be explained by the screw dislocation theory. The microcone-structured surface exhibited a water contact angle of up to 127 degrees, significantly higher than that of flat Ni-P coatings (<110 degrees), demonstrating the efficacy of the microstructure in enhancing surface hydrophobicity. This work provides a viable and scalable strategy for fabricating functional Ni-P microcone coatings.

As promising candidates for high-performance power system applications, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have garnered significant attention from the market. However, reliability challenges, particularly under real-world operating conditions involving multi-stress scenarios, remained to be thoroughly investigated. This study systematically examined the impact of varying levels of power cycling (PCT) degradation on the short-circuit (SC) ruggedness of 1.2 kV SiC MOSFET power modules. The changes in DC parameters and defect density during the multi-stresses were quantitatively analyzed, and the failure mechanism was validated through simulations. Additionally, the results revealed that the short-circuit withstand time (SCWT) decreased significantly with progressive levels of PCT aging. This work provides insights into the reliability and operational lifespan of SiC MOSFET under real-world operating conditions.

With the advancement of packaging technology, Cu-Cu direct interconnection has become a major research focus. Electroplating bonding enables Cu-Cu interconnection at room temperature without applied pressure, offering lower bonding temperatures compared to other low-temperature Cu-Cu bonding techniques. However, achieving uniform and dense plating growth remains the core challenge of this technology. This study proposes an electroplating bonding process for micro copper pillar array interconnections and conducts finite element simulations and electroplating bonding experiments using an accelerator-suppressor-leveler (ASL) system. The results show that the ASL system produces conformal deposition characteristics due to the high coverage and uniform distribution of levelers and suppressors in the bonding area. The Janus Green B (JGB) system produces rough plating contours with poor bonding quality, while both Dodecyl trimethyl ammonium chloride (DTAC) and 4,6-dimethyl-2-mercaptopyrimidine (DMP) systems yield well-defined plating profiles with superior bonding performance. However, due to the excessive plating thickness in the DMP system, the DTAC system was selected for the temperature cycling test. The results showed that after 100 thermal cycles, the average shear strength of the samples decreased by only 8.35 MPa, and the fracture location remained unchanged, still located at the interface between the plating layer and the lower bump. This indicates that the samples bonded using the DTAC system exhibit good thermomechanical reliability under the given process conditions.

Currently, one of the serious challenges in microelectronic devices is the miniaturization trend of packaging. With the continuous development of microelectronic packaging toward high density and small size, microsolder joints will be subjected to thermal-electrical force and other loads alone or simultaneously under common service conditions, which will cause the failure of the interconnect structure. This study explores interface evolution and failure mechanisms of Sn3.5Ag microcopper pillar solder joints under high current density. Experiments show that at 3 & times;10(4) A/cm(2) and 150( degrees) C, cathode-side Ni layers dissolve rapidly, forming intermetallic compounds (IMCs) such as Cu3Sn and (Cu,Ni)(6)Sn-5, while electromigration-resistant Ag3Sn particles aggregate in the solder core to suppress IMC growth. Kirkendall voids nucleate at the Cu-Cu3Sn interface, evolving into cracks under prolonged current stress. ANSYS simulations reveal severe current crowding at copper pillar-trace interfaces, with peak densities reaching 3.82 & times;10(5) A/cm(2). Shorter substrate-side pillars fail earlier due to nonuniform dissolution, while longer chip-side pillars homogenize current flow. Failure modes shift from cathode-side cracking at low densities to pancake-shaped void formation at high densities, guiding microelectronic packaging optimization for high-current reliability.

Temperature control of samples constitutes a critical aspect in magnetron sputtering processes. Poor surface temperature uniformity can lead to film warping and delamination, ultimately reducing chip production yield. Quartz lamp infrared matrix heating is a widely used method in magnetron sputtering heating systems due to its controllability and ease of adjustment. However, the temperature uniformity across the sample surface is highly sensitive to lamp arrangement, and improper layouts can result in significant temperature gradients. To improve temperature uniformity, we developed a finite element simulation model calibrated with experimental heating data. Based on this model, eight optimized lamp arrangements were designed and simulated. The results indicate that positioning lamps closer to the center enhances the heating rate in the central region and reduces temperature disparities across the sample. An optimal lamp layout was proposed based on simulations, and experimental validation confirmed a 30.27 °C reduction in temperature variation compared to the original setup, demonstrating that surface temperature uniformity is improved by 38%

Purpose While miniaturized pressure sensors are well-established, conventional silicon-based devices suffer from PN junction breakdown at high temperatures, leading to significant performance degradation. Silicon-on-Insulator sensors offer a solution for high-temperature applications but face persistent challenges in doping control, deep silicon etching and high-temperature packaging. These challenges hinder the simultaneous achievement of miniaturization, high-temperature resilience and high performance. This study aims to overcome these limitations by systematically optimizing these critcal manufacturing and packaging processes. Design/methodology/approach In this paper, a backside-sensing miniature flat high-temperature pressure sensor is designed. Through simulations and experiments, the optimal doping process and deep silicon etching process for manufacturing the corresponding presure-sensitive chip are investigated. For the packaging of the pressure-sensitive chip and the extraction of electrical signals, the deep-hole physical vapor deposition technology for the metal seed layer and the high-temperature reliable interconnection surface mount technology are employed to ensure the reliability of the pressure sensor in high-temperature environments. Findings This pressure sensor has an operating temperature range of −55°C to 235°C, a nonlinearity of 0.3% FS and a thermal sensitivity drift of ±0.018%/°C. It demonstrates excellent comprehensive performance, which fully proves that its design is reliable and reasonable. Originality/value Compared with existing studies that mostly focus on the analysis of a single packaging technology for flat pressure sensors, this paper proposes a set of optimization schemes for key steps covering the entire process from chip manufacturing to chip packaging, which effectively improves the overall performance of the sensor.

Methane (CH4) leak monitoring is essential for ensuring the safety of life and property. Based on tunable diode laser absorption spectroscopy (TDLAS), a compact laser sensor was developed for methane detection in relevant industrial scenarios. A near-infrared (NIR) DFB laser centered around 1654 nm was employed. To improve the signal-to-noise ratio (SNR), the second harmonic (2f) signal was denoised using adaptive variational mode decomposition (VMD) based on modal energy criteria combined with wavelet threshold denoising (EVMD-WTD). A correction formula was applied to compensate for temperature-induced measurement errors, enhancing accuracy. Furthermore, the Fungal Growth Optimizer algorithm was used to optimize the hyperparameters of a bidirectional long short-term memory algorithm (FGO-BiLSTM), enabling high-precision gas concentration inversion. Experimental results demonstrated that the system exhibits good stability and fast response. A minimum detection limit (MDL) of 0.197 ppm & sdot;m was achieved at an integration time of 76 s. This study confirms the feasibility of achieving high-performance methane detection under limited hardware and low-cost conditions through advanced signal processing and concentration inversion methods, offering promising engineering applicability.

Tunable diode laser absorption spectroscopy (TDLAS), with its strong selectivity, high sensitivity, and fast response speed, has become a widely used measurement technique of gas concentration. However, according to the gas absorption spectral theory, variations in temperature and pressure can alter the absorption spectral lines, leading to significant measurement deviation. In this study, based on the TDLAS/wavelength modulation spectroscopy (WMS) measurement system, the effects of temperature and pressure variations on concentration measurement and the second harmonic signal are analyzed. To address these challenges, we propose the multilayer perceptron optimized by fungal growth optimization (FGO-MLP), a lightweight deep learning algorithm that adaptively optimizes the network architecture by integrating FGO with an MLP. The model is trained using temperature, pressure, and key second harmonic spectral features as input variables. Experimental results demonstrate that temperature and pressure perturbations significantly alter the harmonic signals, thereby affecting concentration prediction accuracy. Compared with conventional optimization algorithms, the FGO algorithm provides more effective hyperparameter tuning for the MLP model, resulting in improved predictive performance. On the test set, the proposed model achieves a mean absolute percentage error (MAPE) of 0.97% and a coefficient of determination (R2) of 0.99991. The model maintains low computational complexity, with an average inference time of 0.34 μs per sample. Allan-Werle deviation analysis further confirms the robustness and generalization capability of the proposed approach. These findings provide reliable technical support and practical value for achieving efficient, stable, and precise gas concentration measurements in complex environments using TDLAS systems.

Tunable diode laser absorption spectroscopy (TDLAS), owing to its high selectivity, sensitivity, and fast response, has been widely employed for monitoring methane leakage in urban natural gas pipelines. However, variations in ambient temperature and pressure can alter the absorption spectral lines, thereby reducing the accuracy of concentration measurements. To address this issue and improve measurement reliability, a 1654 nm DFB laser was adopted as the light source, and methane (CH4) at different concentrations was used as the target gas for testing under conditions of 263-323 K and 0.6-1.1 atm. To handle temperature effects, we developed two corrections: one for direct absorption spectroscopy (DAS) that integrates line-strength variation with a systemerror compensation coefficient, and another for wavelength modulation spectroscopy (WMS) based on dualpeak combined intensity, while pressure effects were mitigated via a least-squares correction. The temperature correction reduced the maximum relative errors of DAS and WMS from about 30 % and 20 % to around 2 %, respectively, while the pressure correction decreased the maximum relative error from 3.69 % to 1.05 %. Allan deviation analysis indicated that the sensor achieved a minimum detection limit (MDL) of 4.41 ppm at an integration time of 30 s. In a 24-hour continuous monitoring test conducted under fluctuating temperature conditions, the maximum relative errors for measuring 1 x 104 ppm CH4, after applying the correction formulas, were reduced to 1.92 % for DAS and 0.84 % for WMS. This study provides a novel and effective approach to enhancing gas concentration measurement accuracy in urban natural gas pipeline leakage detection and related industrial applications.

The vacuum degree in the cavity of the electron beam evaporation coating equipment and the time taken to reach the vacuum are the key factors to measure the quality of the equipment. The shutter structure in the exhaust pipe can prevent the discharge of metal vapor molecules, but it will also hinder the discharge of air during vacuum. In order to improve the pumping performance of the equipment, a finite element simulation model was established based on comsol multiphysics simulation software. In this paper, this model is applied to investigate the influence of the louver blade structure in the pumping pipeline on the system's performance. A parametric study was conducted by simulating the vacuuming process under different angles and quantities of blades. The results show that the larger the angle of the blades and the fewer the number of blades, the higher the efficiency of air extraction. Vacuum experiments were conducted using a high-precision multilayer metal evaporation semiconductor equipment to verify the accuracy of the simulation model. This study makes the vacuuming process of semiconductor equipment clearer and provides data support for the design and selection of the louver blades in the pipelines of evaporation coating equipment.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are increasingly operated under fast-switching conditions, making dynamic reliability evaluation indispensable. This paper investigates the threshold voltage (VTH) shift and gate oxide failure of 1.2 kV SiC MOSFETs under dynamic reverse bias (DRB) and the effect of dynamic gate bias (DGB) pre-stress. The results show that dVDS/dt-induced VGS transients and displacement currents drive positive charge generation at the SiC/SiO2 interface, causing negative VTH shift under DRB single stress. DGB pre-stress modifies shallow near-interface defects and induces electron trapping, leading to negative charge accumulation and a positive VTH shift during subsequent DRB. Deep-level transient spectroscopy (DLTS) results further reveal deeper defect levels and enhanced charge trapping under DRB single stress, but with less severe IGSS- degradation under combined stress. These findings provide crucial insights into the reliability of SiC MOSFETs under realistic fast-switching operating conditions.

Controllable filler distribution to construct thermal conductive pathways is critical for optimizing polymer composite thermal conductivity. Herein, FDM 3D printing was utilized to precisely regulate the orientation of boron nitride (BN) microplatelets in thermoplastic polyurethane (TPU), and spherical alumina (Al2O3) was co-filled as a thermal conductive bridge between oriented BN to construct a thermal conductive network under the action of structural complementarity. Meanwhile, we systematically revealed the synergistic effect of hybrid fillers with different proportions and contents, and further explored the regulation mechanism of printing process parameters on the thermal conductive network and properties of composites. It was found that the shear and compression effects during the extrusion and deposition of composite melt could induce the oriented arrangement of BN along the printing plane, and an appropriate proportion of Al2O3 could not only enhance the orientation of BN but also act as an effective bridge to connect BN. In addition, a smaller nozzle diameter and layer height were proven to provide a greater effect on the melt shear flow, which is conducive to the formation of a highly oriented filler network. Therefore, the thermal conductivity of BN/Al2O3/TPU with the highly oriented BN/Al2O3 network reaches 2.73 W/m K, which is 1.16 times that of BN/TPU and 13.65 times that of pure TPU, accompanied by excellent thermomechanical properties, and holds great significance in the electronic device thermal management.

The liquid level in flotation processes significantly impacts the recovery rate and grade of minerals. The flotation environment presents particularly challenging conditions for measurement, characterized by the presence of abundant bubbles, suspended mineral particles, and frequently acidic pulp. Under these conditions, conventional liquid level sensors are prone to measurement inaccuracies, and their probes are highly susceptible to corrosion. To address these limitations, this paper proposes an extended differential pressure method for liquid level detection. The proposed approach employs four hydraulic detection points and accounts for the gas content in the slurry. Compared with the traditional two-point differential pressure method, this technique demonstrates enhanced accuracy in liquid level calculation. Based on the extended differential pressure method, a level sensor with four isolated probes for the flotation environment was developed. It uses air pressure to measure the hydraulic pressure, thereby avoiding direct contact between the probes and the slurry. An experimental platform was constructed to simulate the flotation environment. On this platform, the level sensor was tested and calibrated. The liquid level calculation algorithm was optimized through interpolation of existing experimental data. The optimized detection error was maintained within +/- 1 cm.

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) increasingly operate under high voltage and fast switching conditions, making dynamic reverse bias (DRB) testing essential for evaluating their reliability. This letter presents a failure behavioral process and mechanism of 1.2 kV SiC MOSFETs under DRB stress. The observed failure mode was gate oxide breakdown, attributed to gate crosstalk caused by dVDS/dt-induced displacement current during rapid VDS transitions. This study reveals the dynamic evolution process of carriers and electric field at the SiC/SiO2 interface under DRB timing sequence. The leakage path induced by DRB stress was characterized by IGSS-, IDSS, and failure analysis. TCAD simulations revealed that the electric field gradually accumulated during DRB stress, with the highest field appearing at the edge of the gate oxide. These findings provide crucial insights into DRB induced failure and offer a practical framework for the reliability assessment of SiC MOSFETs.

The design and preparation of polymer composites for microelectronic package with high thermal conductivity is an important route to solve the thermal problem of electronic devices. The synergistic effect of interface heat transfer and hybrid filler structure on the enhancement of thermal conductivity in polyurethane composites was analyzed using a multiscale approach. Firstly, the interface heat transfer characteristics and strengthening mechanism of BN-TPU and Al2O3-TPU regulated by functionalization were analyzed by atomic scale calculation. Then, the thermal conductivity of BN/Al2O3/TPU composites under different interface thermal resistance, filler distribution, filler ratio and contents were studied through representative volume elements with interface layer structure. The results indicate that, due to the functionalized molecules increasing the phonon vibration overlap between the filler and matrix and thereby reducing the interface thermal resistance, the thermal conductivity of the composite materials shows an increasing trend with interface functionalization. Moreover, under the combined effects of constructing oriented BN structures, optimizing the ratio between BN and Al2O3, and regulating interface functionalization, the composites showed excellent thermal conductivity at low filler content. The research can provide important guidance for the preparation of highly thermal conductive polymer composites.

Purpose The purpose of this paper is to reduce the problem of temperature drift causing output errors in such sensors, three hardware compensation schemes are proposed in this paper, and three compensation schemes are designed and implemented. Design/methodology/approach In response to the problem of temperature drift causing output errors in this type of sensor, this paper proposes three hardware compensation schemes and carries out the design and implementation of the three compensation schemes. Finally, the advantages and disadvantages of the three compensation schemes are discussed through the analysis of the experimental results. The three hardware compensation methods are series-parallel resistance network compensation, digital signal processor (DSP) compensation and the joint compensation of resistance network and DSP. Series parallel resistance network compensation is to connect the low-temperature drift resistance and the sensor in series and parallel; DSP compensation is based on the combination of cubic spline interpolation and linear fitting algorithm, which uses DSP to process the data. Joint compensation is a new compensation method composed of the above two compensation methods. Findings The experimental results show that the relative error of the output is reduced to a certain extent after the three compensation methods, and the relative error of the output after the joint compensation is reduced to about 0.2%, which proves that the three compensation methods are feasible. Originality/value This paper presents three novel hardware compensation methods to reduce temperature drift in silicon on insulator (SOI) high-temperature pressure sensors. The joint compensation method, combining resistance network and DSP compensation, is particularly innovative and significantly improves output accuracy, reducing relative error to about 0.2%.

Purpose The purpose of this study is to explore simulation-based methods for enhancing the sensitivity of pressure-sensitive chips, aiming to reduce design time and overall development costs. Design/methodology/approach First, the factors influencing the sensitivity of Silicon On Insulator (SOI) pressure-sensitive chips are analyzed. These factors primarily include the crystal orientation of the chip material, impurity concentration, the position of the piezoresistor on the chip surface and the dimensions of the piezoresistor grid. An analysis model of the SOI pressure-sensitive chip is then established using COMSOL simulation software. Through electromechanical coupling simulations, sensitivity data under various parameters are obtained, with the factors affecting sensitivity serving as model adjustment parameters. The main parameters influencing the sensitivity of SOI pressure-sensitive chips and their respective range values are summarized. Findings A simulation method is developed to study the influence of crystal orientation, doping concentration, piezoresistor position and size on the sensitivity. The simulation results from the typical model align well with theoretical predictions, demonstrating that the method presented in this paper can effectively optimize sensitivity design during the design phase of pressure-sensitive chips. Originality/value This paper summarizes the factors affecting the sensitivity of SOI pressure-sensitive chips, presents a simulation model and method for optimizing pressure-sensitive chip design and simulates the optimal parameter ranges to enhance sensitivity.

Achieving precise thermal control over large substrates remains a critical challenge in molecular beam epitaxy (MBE) systems, where conventional single-temperature zone heaters often fail to deliver uniformity under high-temperature and ultra-high vacuum conditions. This study introduces a novel dual-temperature zone heater architecture for large-scale MBE, integrating multi-layer insulating and reflecting plates to address non-uniform heat distribution. A coupled electrical-thermal-mechanical simulation framework is established to capture multi-physics interactions, enabling structure optimization beyond traditional empirical tuning. Furthermore, a predictive modeling approach systematically links geometric parameters to thermal uniformity, providing a quantitative basis for refining the design. Experimental results show that the heater maintains a substrate temperature difference within +/- 3 K at the target temperature of 983 K, with a maximum achievable temperature of 1275 K and a simulation-to-experiment maximum deviation of 2.4 K. These findings confirm the reliability of the proposed co-design methodology and demonstrate a substantial improvement in uniformity compared with conventional designs. The proposed strategy offers a scalable framework for next-generation high-precision thermal control in MBE and related large-scale deposition systems.

With the increasing interconnect density of electronic components, copper-copper direct bonding technology has garnered increasing attention from researchers. The electroplating bonding method is an efficient copper pillar interconnection technique that can be implemented at room temperature and atmospheric pressure. comsol simulation results show that under convective conditions, the plating layer primarily deposits on the convection exit side of the copper plate. Under weak convection and low current density, the plating exhibits deposition characteristics that conform to the substrate surface. As convection intensity increases, preferential deposition begins to occur, although the overall deposition rate decreases. At this point, when the current density is increased, the deposition pattern predominantly shows preferential deposition; however, excessively high current density can lead to copper deposition in nonbonding areas. Orthogonal experimental results indicate that, within the accelerator bis(3-sulfopropyl) disulfide (SPS)-inhibitor polyethylene glycol (PEG)-leveling agent Jenner Green B (JGB)-chloride ion (Cl-) system, the influence of the four additives on bonding strength follows this order: JGB > Cl- > SPS > PEG. The optimal formulation derived from the orthogonal experiments is SPS 2 ppm, PEG (8000) 150 ppm, JGB 5 ppm, and Cl- 30 ppm, which results in a shear strength of 123.2 MPa. These findings suggest that high-strength copper pillar interconnections can be achieved by adjusting physical parameters such as the electric field, flow field, and additive concentrations.