A description is given of the R3010 floating-point accelerator chip, a coprocessor that is based on advanced reduced-instruction-set-computer (RISC) architecture and VLSI design techniques and provides high-speed floating-point operation. The 75000-transistor hard-wired chip executes four instructions in parallel. Its performance is compared with that of available floating-point processors and its architecture is examined. The organization and implementation of the R3010 is discussed.

A new system for logic synthesis and VLSI layout, the Stanford Weinberger Array Minimizer and Implementor (SWAMI), has been developed. This paper describes the system's algorithms and presents preliminary results. The minimization of logic expressions uses local sum-of-products minimization, kernel factorization and common subexpression recognition and generates improved expressions of arbitrary depth. Logic expressions are realized in nMOS technology using one dimensional Weinberger array structures or a new extension of Weinberger arrays to two dimensions. The placement phase uses heuristic techniques, including simulated annealing, MIN-CUT linear arrangement and local constructive clustering.

Current VLSI fabrication technology makes it possible to design a 32-bit CPU on a single chip. However, to achieve high performance from that processor, the architecture and implementation must be carefully designed and tuned. The MIPS processor incorporates some new architectural ideas into a single-chip, nMOS implementation. Processor performance is obtained by the careful integration of the software (e.g., compilers), the architecture, and the hardware implementation. This integrated view also simplifies the design, making it practical to implement the processor at a university.

MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.